US 5,493,660 A · Software assisted hardware TLB miss handler

Abstract

The present invention provides a software-assisted hardware TLB miss-handler which is designed to reduce the TLB miss penalty while being low cost to implement and requiring little chip area or complexity. When a TLB miss occurs, the HW TLB miss handler of the present invention computes a physical address of a page table entry located in a special hardware-visible table based on a missing virtual address. It accesses the page table entry and checks for a correct translation and status information. If correct, a physical page address and protection information of the page table entry are inserted into the TLB. The original virtual address is re-translated and normal program execution continues. If the correct translation and status are not found, the HW TLB miss-handler will not insert the entry and will trap to a more sophisticated SW TLB miss handler. A pointer to the page table entry is passed to the SW TLB miss handler so that the page table address need not be recomputed. Thus, the HW TLB miss-handler of the present invention services the simplest and most common TLB misses very quickly, reducing the overall TLB miss penalty. The slower SW TLB miss handler services the more complex and less common TLB misses and provides flexibility in the virtual memory management system.

Claims2

Dependent claims

A computer-based system for handling translation lookaside buffer (TLB) misses, the system comprising:

a memory unit for storing blocks of dam, wherein each block of data is accessed via a virtual address;
a TLB for storing address translation information for translating said virtual address to a physical address for each block of data in said memory unit;
a hardware TLB miss handler, coupled to said TLB, adapted to hash said virtual address to form a physical address pointer into a physical page directory, and further adapted to check a hardware-visible portion of said physical page directory for a missing translation, wherein said hardware TLB miss handler comprises:
hashing means for hashing said virtual address to form a first pointer by XORing the most significant bits of said virtual address with the least significant bits of said virtual address;
masking means for performing a bitwise logical AND function on said first pointer and a mask register to form a second pointer, and
merging means for performing a bitwise logical OR function on said second pointer and the most significant bits of a base-address register to form said physical address pointer;
and
a software TLB miss handler adapted to accept said physical address pointer from said hardware TLB miss handler if said hardware TLB miss handler does not locate the missing translation in the hardware-visible portion of said physical page directory, said software TLB miss handler further adapted to check the remainder of said physical page directory for the missing translation.

5 more elements

Dependencies are inferred from the claim text.

Software assisted hardware TLB miss handler

Life of this patent

Software assisted hardware TLB miss handler

Life of this patent

Abstract

Claims2