Data processor providing fast break in program execution

A data processing system comprising:

• a target processor on a single chip for performing operations in response to execution of programs of instructions forming a user space;
• and
• a main processor coupled to said target processor for performing operations as an in-circuit emulator, including input means for inputting a break command and a break address, and break circuit means responsive to said break address and an address signal received from said target processor for generating a break signal;
• wherein said target processor includes an instruction register for holding an instruction to be executed;
• fetch means for applying instructions in sequence to said instruction register;
• decoding means for decoding an instruction held in said instruction register and for producing control signals based on the decoded instruction;
• bus means for supplying data and instructions;
• and execution means responsive to said control signals produced by said decoding means for performing an arithmetic operation on data received on said bus means;
• wherein said fetch means includes memory circuit means for storing only an interrupt instruction and switching means connected to said memory circuit means and said bus means and responsive to the absence or presence of said break signal from said break circuit means for selectively applying either an instruction received on said bus means or said interrupt instruction from said memory circuit means to said instruction register.

An integrated microprocessor having first and second operating modes comprising:

• a processor for executing a first predetermined data processing according to a program to be developed in the first operating mode, and executing a second predetermined data processing according to an emulator program in the second operating mode;
• a control signal input terminal for receiving an externally generated break signal having a first state and a second state, and means for changing the operation of the processor to the second operating mode from the first operating mode in response to said externally generated break signal changing from the first state to the second state;
• and
• an output terminal for providing an internally generated break acknowledge signal which has a first level when the processor is in the first operating mode, and a second level when the processor is in the second operating mode, and which is provided from the processor.

An integrated microprocessor, comprising:

• first input terminals for receiving mode control signals;
• mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode;
• a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the mode determining means provides the emulator mode signal;
• means, including a second input terminal for receiving a break signal having a first state and a second state, for changing operation of the processor to the second operating mode from the first operating mode in response to receipt of a break signal changing from the first state to the second state;
• and
• a gate circuit coupled to the second input terminal and to the mode determining means and for validating the break signal on the second input terminal only when the mode determining means generates the emulator mode signal.

An integrated microprocessor, comprising:

• first input terminals for receiving mode control signals;
• mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode;
• a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the integrated microprocessor is in the emulator mode, wherein the program to be developed includes a break instruction for changing the operation mode of the processor from the first operating mode to the second operating mode, wherein the operation mode of the processor is changed to the second operating mode from the first operating mode in response to execution of the break instruction by the processor;
• and
• check means coupled to the mode determining means for producing an output as to whether or not the integrated microprocessor is in the emulator mode and for sending said output to the processor when the check means receives a check request signal from the processor;
• wherein the processor executes the break instruction after the processor receives the output indicating that the integrated microprocessor is in the emulator mode from the check means.