Microcomputer with dynamic bus controls

A single-chip microcomputer formed on a single-chip, comprising:

• an address bus;
• external address terminals coupled to the address bus;
• a data bus including first data lines and second data lines;
• first and second external data terminals, a number of which is identical to that of the first and second data lines;
• a processor unit which is coupled to the address bus and to the data bus and which provides an address signal to the address bus to access an address designated by the address signal, wherein the processor unit accesses an address in a predetermined address space;
• and
• a data circuit which is coupled to the address bus, to the data bus and to the first and second external data terminals and which includes:
• a bus control circuit including a first circuit which indicates a first address area in the predetermined address space and a first detection circuit which detects whether or not the address signal provided from the processor unit designates an address in the first address area;
• a data input/output circuit which couples each of the first data lines and the second data lines to the first external data terminals in sequence in response to the detection of the address in the first address area by the bus control circuit and which couples the first data lines and the second data lines to the first external data terminals and the second external data terminals, respectively, in response to no detection of the address in the first address area by the bus control circuit;
• and
• a wait control circuit including a second circuit which indicates a second address area in the predetermined address space and a second detection circuit which detects whether or not the address signal provided from the processor unit designates an address in the second address area, wherein the processor unit accesses the address designated by the address signal in accordance with bus cycles having a predetermined number in response to detection of the address in the second address area from the second detection circuit and wherein the processor unit accesses the address designated by the address signal in accordance with bus cycles having a different number from the predetermined number in response to no detection of the address in the second address area from the second detection circuit.

A data processing system comprising:

• a single-chip microcomputer having external address terminals, first external data terminals and second external data terminals;
• an external address bus coupled to the external address terminals;
• an external data bus including first external data lines coupled to the first external data terminals, respectively and second external data lines coupled to the second external data terminals, respectively;
• a first external device coupled to the external address bus and to the first external data lines;
• and
• a second external device coupled to the external address bus and to the first and second external data lines,
• wherein the single-chip microcomputer further includes:
• an internal address bus coupled to the external address terminals;
• an internal data bus including first internal data lines and second internal data lines, a number of the first and second internal data lines being identical to that of the first and second external data terminals;
• a processor unit coupled to the internal address bus and to the internal data bus, the processor unit providing an address signal to the internal address bus to access an address in a predetermined address space designated by the address signal, wherein the predetermined address space includes a first address area where an address of the first external device is assigned and a second address area where an address of the second external device is assigned;
• and
• a data circuit coupled to the internal address bus, to the internal data bus and to the first and second external data terminals and including:
• a bus control circuit including a circuit which indicates the first address area in the predetermined address space and a detection circuit which detects whether the address signal provided from the processor unit designates an address in the first address area or in the second address area;
• and
• a data input/output circuit which couples each of the first internal data lines and the second internal data lines to the first external data terminals in sequence in response to the detection of the address in the first address area by the bus control circuit and which couples the first internal data lines and the second internal data lines to the first external data terminals and the second external data terminals, respectively, in response to the detection of the address in the second address area by the bus control circuit.