Pixel block transfer with transparency

An integrated circuit comprising on a single semiconductor chip:

• an internal memory having a plurality of storage locations;
• a data processor connected to said internal memory for data manipulation of data stored in said internal memory;
• an external memory interface for data communication to an external memory;
• a data transfer controller connected to said internal memory, said data processor and said external memory interface, said data transfer controller responsive to said data processor for controlling transfer of data from a specified block of source addresses to a specified block of destination addresses, said data transfer controller including
• a transparency register storing transparency data, said transparency register storing a multiple of a multibit minimum amount of data to be transferred,
• a comparator coupled to said transparency register, said comparator comparing said data to be transferred with said transparency data stored in said transparency register in units of said multibit minimum amount of data to be transferred and providing a plurality of indications whether said data to be transferred is to be written to the external memory, one indication for each unit of said multibit minimum amount of data to be transferred, and
• a memory write signal generator connected to said external memory interface and said comparator for generating a write signal enabling data to be written into the external memory for each unit of said minimum amount of data to be transferred if said comparator indicates said corresponding data to be transferred is to be written to the external memory.

A data processing system comprising:

• a data processing system bus transferring data and addresses;
• a system memory connected to said data processing system bus, said system memory storing data and transferring data via said data processing system bus;
• an data processor circuit connected to said data processing system bus, said data processor circuit including
• an internal memory having a plurality of storage locations;
• a data processor connected to said internal memory for data manipulation of data stored in said internal memory;
• a data processing system bus interface for data communication to said system memory;
• a data transfer controller connected to said internal memory, said data processor and said system memory interface, said data transfer controller responsive to said data processor to transfer data from said internal memory to said system memory interface for writing in said system memory, said data transfer controlling including
• a transparency register storing transparency data, said transparency register storing a multiple of a multibit minimum amount of data to be transferred,
• a source address controller coupled to said internal memory, said source address controller calculating source addresses and recalling data to be transferred from said internal memory at storage locations corresponding to said source addresses,
• a comparator coupled to said transparency register and said source address controller, said comparator comparing said data to be transferred with said transparency data stored in said transparency register in units of said multibit minimum amount of data to be transferred and providing a plurality of indications whether said data to be transferred is to be written to said system memory, one indication for each unit of said minimum amount of data to be transferred,
• a destination address controller coupled to said comparator calculating destinations addresses, said destination address controller supplying data to be transferred to said system memory interface at storage locations corresponding to said destination addresses, and
• a memory write signal generator connected to said data processing system bus interface and said comparator for generating a write signal enabling data to be written into said system memory for each unit of said minimum amount of data to be transferred if said comparator indicates said corresponding data to be transferred is to be written to said system memory.

A data processor comprising:

• a memory having plurality of storage locations;
• a data transfer controller coupled to said memory controlling transfer of data from a specified block of source addresses to a specified block of destination addresses, said data to be transferred being organized into data words having a selected size, said selected size being integral multiples of a multibit minimum amount of data to be transferred, said data transfer controller including
• a transparency register storing transparency data, said transparency register storing a multiple of said multibit minimum amount of data to be transferred,
• a comparator coupled to said transparency register, said comparator including
• a plurality of data comparators, each data comparator comparing said multibit minimum amount of data to be transferred with a corresponding part of said transparency data stored in said transparency register and detecting whether said multiple minimum amount of data to be transferred matches said corresponding part of said transparency data stored in said transparency register,
• a multiplexer connected to said plurality of data comparators and receiving an indication of said selected data size, said multiplexer providing a number of said indications of whether said data to be transferred is to be written to said memory equal to a number of times said data words of said selected size fit within said transparency register, said number of indications formed from said detected matches and said selected data size;
• and
• a memory write signal generator connected to said memory and said comparator for generating a write control signal enabling data to be written into said memory for each unit of said selected data size to be transferred if said comparator indicates said corresponding data to be transferred is to be written to said memory.

An integrated circuit comprising on a single semiconductor chip:

• an internal memory having a plurality of storage locations;
• a data processor connected to said internal memory for data manipulation of data stored in said internal memory;
• an external memory interface for data communication to an external memory;
• a data transfer controller connected to said internal memory, said data processor and said external memory interface, said data transfer controller responsive to said data processor for controlling transfer of data from a specified block of source addresses to a specified block of destination addresses, said data transfer controller including
• a transparency register storing transparency data, said transparency register storing a multiple of a multibit minimum amount of data to be transferred,
• a comparator coupled to said transparency register, said comparator including
• a plurality of data comparators, each data comparator comparing said multibit minimum amount of data to be transferred with a corresponding part of said transparency data stored in said transparency register and detecting whether said multiple minimum amount of data to be transferred matches said corresponding part of said transparency data stored in said transparency register,
• a multiplexer connected to said plurality of data comparators and receiving an indication of said selected data size, said multiplexer providing a number of said indications of whether said data to be transferred is to be written to the external memory equal to a number of times said data words of said selected size fit within said transparency register, said number of indications formed from said detected matches and said selected data size;
• and
• a memory write signal generator connected to said external memory interface and said comparator for generating a write signal enabling data to be written into the external memory for each unit of said minimum amount of data to be transferred if said comparator indicates said corresponding data to be transferred is to be written to the external memory.

A data processing system comprising:

• a data processing system bus transferring data and addresses;
• a system memory connected to said data processing system bus, said system memory storing data and transferring data via said data processing system bus;
• an data processor circuit connected to said data processing system bus, said data processor circuit including
• an internal memory having a plurality of storage locations;
• a data processor connected to said internal memory for data manipulation of data stored in said internal memory;
• a data processing system bus interface for data communication to said system memory;
• a data transfer controller connected to said internal memory, said data processor and said system memory interface, said data transfer controller responsive to said data processor to transfer data from said internal memory to said system memory interface for writing in said system memory, said data transfer controlling including
• a transparency register storing transparency data, said transparency register storing a multiple of a multibit minimum amount of data to be transferred,
• a source address controller coupled to said internal memory, said source address controller calculating source addresses and recalling data to be transferred from said internal memory at storage locations corresponding to said source addresses,
• a comparator coupled to said transparency register and said source address generator, said comparator including
• a plurality of data comparators, each data comparator comparing said multibit minimum amount of data to be transferred with a corresponding part of said transparency data stored in said transparency register and detecting whether said multiple minimum amount of data to be transferred matches said corresponding part of said transparency data stored in said transparency register,
• a multiplexer connected to said plurality of data comparators and receiving an indication of said selected data size, said multiplexer providing a number of said indications of whether said data to be transferred is to be written to the external memory equal to a number of times said data words of said selected size fit within said transparency register, said number of indications formed from said detected matches and said selected data size, and
• a destination address controller coupled to said comparator calculating destinations addresses, said destination address controller supplying data to be transferred to said system memory interface at storage locations corresponding to said destination addresses, and
• a memory write signal generator connected to said data processing system bus interface and said comparator for generating a write signal enabling data to be written into said system memory for each unit of said minimum amount of data to be transferred if said comparator indicates said corresponding data to be transferred is to be written to said system memory.