Circuit arrangement for synchronizing a data stream

A circuit arrangement for synchronizing successive, low sampling rate samples of a data stream converted from a high sampling rate to the low sampling rate and represented as a sequence of samples of a signal with a first synchronizing signal (SM) contained in the high sampling rate data stream, comprising:

• a memory cyclically written and read in an equidirectional address sequence and which receives write address signals for writing the samples of the high sampling rate data stream from a write address counter which counts periods of a first sampling clock signal having the high sampling rate, means for supplying read address signals to the memory for reading samples of the equally high sampling rate data stream from a combination circuit in which the read address signals are derived from an additive combination of the write address signals with a difference address signal received from an arrangement for forming the difference address signal, wherein the arrangement for forming the difference address signal comprises a modulo counter for counting the periods of the first sampling clock signal, a first sample-and-hold circuit for storing the count (PHI) of the modulo counter in response to the first synchronizing signal, and an allocating circuit which receives the count (PHI) stored in the first sample-and-hold circuit and supplies the combination circuit with a value of the difference address signal at each of these counts (PHI), at which value the write address counter has a larger modulus (S) than the modulo counter, and the modulus (P) of the modulo counter corresponds to an integral ratio between the high and the low sampling rates, a decoding circuit coupled to the modulo counter for supplying a second sampling clock signal having the low sampling rate whenever the modulo counter assumes a basic state, and a second sample-and-hold circuit for storing a sample which is read from the memory by means of the read address signal and at the instant of occurrence of the second sampling clock signal and for supplying the samples thus stored as the low sampling rate data stream.