Loading patent…
AssigneeFrance Telecom
InventorsPierre Boyer, Olivier Dugeon, Michel Servel
Estimating the term…
A data transmission system has a time interval allocation system with a time interval management unit (UGIT) and a plurality of counters (CSO.sub.1 to CSO.sub.n) connected to one another in a cascaded series. The input of a counter (CSO.sub.i) is connected to the output of the preceding counter (CSO.sub.i-1) in the series. The input of the first counter (CSO.sub.1) is connected to the output of the time intervals management unit. Each counter (CSO.sub.i) is associated with an input carrying a time interval allocation demand signal (dem.sub.i) and provided with a command input for receiving the allocation demand signal (dem.sub.i) and delivering either the time interval value (ITin) present on its input if the allocation demand signal (dem.sub.i) is inactive, or the time interval value present on its input increased by a unit (ITin+1) if the demand signal (dem.sub.i) is active. The output of each counter (CSO.sub.i) is connected to the input of a register (RegAd.sub.i), having a command input for receiving the corresponding demand signal (dem.sub.i). Then, each register (RegAd.sub.i ) delivers an allocated time signal (ITa) if the corresponding demand signal (dem.sub.i) is active.
A time interval allocation system comprising a time intervals management unit (UGIT) for delivering at each time interval a signal representative of a last time interval which has been allocated, a plurality of counters (CSO.sub.1 to CSO.sub.n) connected to one another in a cascaded series so that an input of one counter (CSO.sub.i) is connected to an output of the preceding counter (CSO.sub.i-1) in the cascaded series, the input of a first counter (CSO.sub.1) in said cascaded series being connected to an output of the time interval management unit and the output of a last counter (CSO.sub.n) being coupled to an input of said time interval management unit (UGIT), each of said counters (CSO.sub.i) being associated with an input carrying a time interval allocation demand signal (dem.sub.i) and having a command input for receiving the allocation demand signal (dem.sub.i) and for delivering either a time interval value (ITin) present on its input if the allocation demand signal (dem.sub.i) is inactive or the time interval value present on its input increased by a unit (ITin+1) if the demand signal (dem.sub.i) is active, a register individually associated with each of said counters, and means for connecting the output of each of said counters (CSO.sub.i) to an input of a corresponding register (RegAd.sub.1), the register having a command input for receiving the demand signal (dem.sub.i) supplied to the corresponding counter, the register (RegAd.sub.i) then delivering an allocated time interval signal (ITa) if said corresponding demand signal (dem.sub.i) is active.
A time interval allocation system comprising a time interval management unit (UGIT) for delivering at each time interval a signal representative of a last time interval which has been allocated, and a plurality of groups of input circuits (GRCE.sub.1 to GRCE.sub.n) connected to one another in a cascaded series so that an input of one group (GRCE.sub.i) is connected to an output of the preceding group (GRCE.sub.i-) in the cascaded series, the input of a first group in said cascaded series being connected to an output of the time interval management unit (UGIT) and the output of a last group being coupled to an input of the time interval management unit, each of said groups (GRCE.sub.i -GRCE.sub.n) including a plurality of adders (Add.sub.i) arranged in rows and a summation circuit (Som, Som.sub.i), each adder having a first input connected to an input (Cin) of a corresponding group (GRCE.sub.i) and being associated with an input carrying a time interval allocation demand signal (dem.sub.i), an adder (add.sub.i) of a row 1 in a given group (GRCE.sub.i) receiving on a second input a signal from the summation circuit (Som, Somm.sub.i) said signal being representative of a number of active allocation demand signals (dem.sub.1 to dem.sub.i-l) present on the inputs associated with adders of preceding rows as well as on the particular input with which it is individually associated, a plurality of registers (RegAd.sub.i) individually associated with said adders, the output of each adder (Add.sub.i) being connected to an input of a corresponding register (RegAd.sub.i), each of said registers having a command input for receiving an associated allocation demand signal (dem.sub.i), each register (RegAd.sub.i) then delivering an allocated time interval signal (IT.sub.i) if said allocation demand signal (dem.sub.i) is active, the output of the last adder (Add.sub.i) of a group (GRCE.sub.i) forming the output of the said group (GRCE.sub.i).
Dependencies are inferred from the claim text.