Apparatus and method for selectively storing error statistics
OwnerWilliam Loinventor
Life of this patent
Estimating the term…
Abstract
A circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure.
Claims19
In a managed repeater having a source port for receiving a data packet, and a repeater front-end for generating a data signal containing a portion of the data packet, a port signal identifying the port number of the source port, and an error signal indicating when the data packet contains an error condition, a circuit for selectively storing an error statistic of the data packet, said circuit comprising:
- a data formatter for receiving the data signal and an error code from the repeater front end and arranging bits of the portion and said error code into a format for transfer from an output of said data formatter;
- a memory, coupled to said output of said data formatter, for storing the portion and said error code upon transfer;
- and
- a controller, coupled to said data formatter and to said memory storage device and responsive to an assertion of the error signal, for synchronously transferring and writing the portion and said error code from said output of said data formatter into said memory.
In a network including a repeater for receiving a data packet at a source port, an improved managing circuit for selectively storing an error statistic of the data packet, said improved managing circuit comprising:
- a repeater front end, coupled to the repeater, for processing the data packet to generate a data signal containing a portion of the data packet, a port signal identifying the port number of the source port, an error status signal identifying an error condition associated with the data packet, an end-of-packet signal indicating an end of the data packet, and an error signal indicating when the data packet contains said error condition;
- a data formatter, coupled to said repeater front end, for receiving said data signal, said port signal, and said error status signal and arranging the bits of said portion, said port number, and said error condition for transfer from an output of said data formatter;
- a memory, coupled to said output of said data formatter, for storing said portion, said port number, and said error condition upon transfer;
- and
- a controller, coupled to said repeater front end, to said data formatter, and to said memory, for synchronously transferring and writing said portion, said port number, and said error condition from said output of said data formatter into said memory, wherein said controller is responsive to the concurrent assertion of said end-of-packet signal and said error signal.
In a network having a data packet received at a source port of a device, a data signal containing a portion of the data packet, a port signal identifying the source port, and an error signal indicating when the data packet contains an error condition, a method for selectively storing an error statistic of the data packet, said method comprising:
- receiving the data signal and an error status signal;
- arranging the bits of the portion and said error status signal into a format for transfer;
- selecting the portion and said error status signal for transfer to storage, wherein said selecting step is responsive to the assertion of the error signal;
- and
- storing the portion and said error status signal upon transfer.
Dependencies are inferred from the claim text.