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US 5,493,538 AGranted
Minimum pulse width address transition detection circuit
AssigneeTexas Instruments Incorporated
InventorDavid W. Bergman
Life of this patent
Estimating the term…
Abstract
A latch circuit is set by a detection circuit which detects a difference between inputs. One of the inputs being delayed by a predetermined period of time. The output of the latch circuit is inverted and delayed through a delay circuit and resets the latch circuit.
Claims14
An address transition detection circuit to detect a change in address for a memory circuit to form an address transition signal comprising:
- an input circuit to input an address transition signal indication of said change in said address;
- a first delay circuit to delay said address transition signal to form a delayed signal;
- a detection circuit to detect a difference between said address transition signal and said delayed signal by forming a difference signal for a sufficient time such that a path to said memory circuit may be precharged;
- and
- a latch circuit to latch said difference signal for a sufficient time so that a path to said memory circuit may be precharged.
2 more elements
An address transition detection circuit to detect a change in address for a memory circuit, comprising:
- an input circuit to input an address transition signal indicative of said change in said address;
- a first delay circuit to delay said address transition signal to form a delayed signal;
- a detection circuit to compare said address transition signal and said delayed signal to form a difference signal in response to a difference between address transition signal and said delayed signal, said circuit including a pull up circuit to form said address transition signal and a pull down circuit to terminate said address transition signal;
- a latch circuit to latch said address transition signal for a sufficient length of time so a path to said memory circuit can be precharged.
1 more element
Dependencies are inferred from the claim text.