Semiconductor memory with edge transition detection pulse disable
AssigneeSGS-Thomson Microelectronics S.A.
InventorDavid C. McClure
Life of this patent
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Abstract
A system and method are provided for disabling the edge transition detection circuit during the flash clear cycle, thereby preventing the generation of an edge transition detection pulse. In a preferred embodiment of the invention, the edge transition detection circuit is connected to the flash clear complement circuitry through a logic gate. During the flash clear cycle, flash clear true, FC.sub.T, is pulled high, flash clear complement, FC.sub.c, is pulled low and inverted to drive a portion of the ETD circuitry high, thereby preventing generation of an ETD pulse during the flash clear cycle.
Claims23
A method of operating an integrated circuit so as to prevent generation of a signal internal to the integrated circuit based upon an edge transition detection pulse, comprising the steps of:
- initiating a flash clear cycle having a flash clear output signal;
- disabling an edge transition detection circuit from generating the edge transition detection pulse responsive to a transition at one of a plurality of inputs of the integrated circuit during operation of said flash clear cycle;
- and
- after completion of said flash clear cycle, enabling said edge transition detection circuit to generate the edge transition detection pulse responsive to a transition at one of the plurality of inputs of the integrated circuit.
A system for disabling a signal path in an integrated circuit device, comprising:
- a first circuit means disposed within the integrated circuit device, for generating an edge transition detection pulse responsive to a transition at one of a plurality of inputs of the integrated circuit device;
- second circuit means for generating a flash clear signal;
- and
- a logic means disposed within the integrated circuit device, having an input connected to said second circuit means to receive the flash clear signal therefrom, and an output connected to said first circuit means, for disabling the first circuit means responsive to receiving the flash clear signal.
A circuit for disabling a signal path in an integrated circuit device, comprising:
- an edge transition detection circuit:
- and
- a logic element having an input connected to receive a flash clear input signal, and having an output connected to said edge transition detection circuit, said logic element for disabling said edge transition detection circuit responsive to receiving the flash clear input signal.
A circuit for disabling a signal path in an integrated circuit device, comprising:
- an edge transition detection circuit, wherein said edge transition detection circuit comprises a plurality of control transistors connected in parallel, each said control transistor having a control electrode, source and drain;
- and
- a logic element having an input connected to receive an input signal, and having an output connected to said edge transition detection circuit, said logic element for disabling said edge transition detection circuit responsive to receiving the input signal,
- wherein the output of said logic element drives the sources of said control transistors to a first logic state.
Dependencies are inferred from the claim text.