Dual-port random access memory having memory cell controlled by write data lines and read enable line

A semiconductor memory circuit having an array of memory cells, each of said memory cells comprising:

• a latch circuit formed of first and second inverters, an input end of said first inverter and an output end of said second inverter being connected in common to a first connection point, and an output end of said first inverter and an input end of said second inverter being connected in common to a second connection point;
• first and second gate elements connected in series, said first and second gate elements being placed between said first connection point and a reference point having a reference electric potential;
• third and fourth gate elements connected in series, said third and forth gate elements being placed between said second connection point and said reference point;
• fifth, sixth and seventh gate elements connected in series, said fifth, sixth and seventh gate elements being placed between said reference point and a read data line;
• a control terminal of said fifth gate element being connected to said latch circuit through one of said first and second connection points;
• said fifth gate element being driven to open or closed according to a data value stored in said latch circuit;
• a read data enable line connected to a control terminal of said sixth gate element, said sixth gate element being driven to open or closed in response to a read data enable signal transferred through said read data enable line;
• a write word line connected to control terminals of said first and fourth gate elements, said first and fourth gate elements being driven to open or closed in response to a select signal transferred through said write word line during a write operation;
• a pair of write data lines through which fata to be stored is written in said latch circuit, one of said pair of write data lines being connected to a control terminal of said second gate element, and the other of said pair being connected to a control terminal of said third gate element;
• said second and third gate elements being driven to open or closed in response to data signals transferred through said pair of write data lines during said write operation, respectively;
• and a read word line connected to a control terminal of said seventh gate element, said seventh gate element being driven to open or closed in response to a read data signal transferred through said read word line during a read operation;
• wherein
• during said write operation, while said first and fourth gate elements and one of said second and third gate elements are driven to closed, said data to be stored is written in said latch circuit through said one of said second and third gate elements which was driven to closed;
• and during said read operation, while keeping said sixth and seventh gate elements closed, said data value stored in said latch circuit is read out through said read data line.