Memory addressing method and apparatus therefor

An addressing method of a memory device having a random port, a serial port and a plurality of cell blocks, whereby the respective cell blocks are alternately addressed, said addressing method comprising the steps of:

• generating an internal row address signal of the upper (n-1)-bit signal by counting a row clock with the value of the n-bit external row address signal as an initial value in response to a row address strobe signal;
• generating a first n-1 bit internal column address signal by counting a first column clock with the value of the upper (n-1)-bit signal of the n-bit external column address signal as an initial value in response to a column address strobe signal;
• generating a second internal column address signal by counting a second column clock with the value of the upper (n-1)-bit signal of the n-bit external column address signals as an initial value in response to said column address strobe signal, and generating a column clock as a selection control signal for selecting input and output signals of said plurality of cell blocks in accordance with the state of the least significant bit signal of said external column address signals;
• receiving and decoding said internal row address signal, thereby addressing row addresses of said plurality of cell blocks simultaneously;
• receiving and decoding said least significant bit signal of said row clock counted value and said first internal column address signal, thereby addressing the column address of one cell block of said plurality of cell blocks;
• receiving and decoding said least significant bit signal of said row clock counted value and said second internal column address signal, thereby addressing the column address of the other cell block of said plurality of cell blocks;
• selecting input and output signals of said plurality of cell blocks in response to said selection control signal;
• generating mutually inverted first and second internal serial clocks from an external serial clock depending on the state of the least significant bit signal of external column address signal in response to said column address strobe signal;
• generating a first serial selection control signal by receiving the least significant bit signal of said row address signal and said first internal column address signal and counting a first internal serial clock with the received value as an initial value;
• generating a second serial selection control signal by receiving the least significant bit signal of said row address signal and said second internal column address signal and counting a second internal serial clock with the received value as an initial value;
• serial-to-parallel converting row data of said one cell block in response to said first serial selection control signal;
• serial-to-parallel converting row data of said another cell block in response to said second serial selection control signal;
• and
• inputting and outputting serially whereby said serial converted serial data pairs are alternately selected in response said serial input and output selection control signal.

A memory device having a plurality of cell blocks, whereby the respective cell blocks are alternately addressed, said memory device comprising:

• internal row address signal generating means for generating an internal row address signal of the upper (n-1)-bit signal by counting a row clock with the value of an n-bit external row address signal as an initial value in response to a row address strobe signal;
• first internal column address signal generating means for generating a first internal column address signal by counting a first column clock with the value of the upper (n-1)-bit signal of n-bit external column address signals as an initial value in response to a column address strobe signal;
• second internal column address signal generating means for generating a second internal column address signal by counting a second column clock with the value of the upper (n-1)-bit signal among said n-bit external column address signals as an initial value in response to said column address strobe signal, and for generating a selection control signal for selecting input and output signals of said plurality of cell blocks by counting a column clock depending on the state of the least significant bit signal of said external column address signals;
• row decoding means for receiving and decoding said internal row address signal, thereby addressing row addresses of said plurality of cell blocks simultaneously;
• first column decoding means for receiving and decoding the least significant bit signal of said row clock counted value and said first internal column address signal, thereby addressing the column address of one cell block of said plurality of cell blocks;
• second column decoding means for receiving and decoding the least significant bit signal of said row clock counted value and said second internal column address signal, thereby addressing the column address of the other cell block of said plurality of cell blocks;
• input/output buffering means for selecting input and output signals of said plurality of cell blocks in response to said selection control signal;
• and
• control signal generating means for generating said row and column address signals, row and column clocks and an internal control signal by receiving internal row and column address strobe signals, external row and column clocks, and an external control signal.

A dual port memory device having a random port, a serial port and a plurality of cell blocks, said dual port memory device comprising:

• internal row address signal generating means for generating an internal row address signal of the upper (n-1)-bit signal by counting row clock with the value of an n-bit external row address signal as an initial value in response to a row address strobe signal;
• first internal column address signal generating means for generating a first (n-1)-bit internal column address signal by counting a first column clock with the value of the upper (n-1)-bit signal of n-bit external column address signals as an initial value in response to a column address strobe signal;
• second internal column address signal generating means for generating a second internal column address signal by counting a second column clock with the value of the upper (n-1)-bit signal of said n-bit external column address signals as an initial value in response to said column address strobe signal, and for generating a selection control signal for selecting input and output signals of said plurality of cell blocks by counting a column clock depending on the state of the least significant bit signal of said external column address signals;
• row decoding means for receiving and decoding said internal row address signal, thereby addressing row addresses of said plurality of cell blocks simultaneously;
• first column decoding means for receiving and decoding the least significant bit signal of said row clock counted value and said first internal column address signal, thereby addressing the column address of one cell block of said plurality of cell blocks;
• second column decoding means for receiving and decoding the least significant bit signal of said row clock counted value and said second internal column address signal, thereby addressing the column address of the other cell block of said plurality of cell blocks;
• input and output buffering means for selecting input and output signals of said plurality of cell blocks in response to said selection control signal;
• serial clock generating means for generating mutually inverted first and second internal serial clocks from external serial clock depending on the state of the least significant bit signal of external column address signal in response to said column address strobe signal;
• first serial selection control signal generating means for generating a first serial selection control signal by receiving the least significant bit signal of said row address signal and said first internal column address signal and counting first internal serial clock with the received value as an initial value;
• second serial selection control signal generating means for generating a second serial selection control signal by receiving the least significant bit signal of said row address signal and said second internal column address signal and counting second internal serial clock with the received value as an initial value;
• first serial-to-parallel converting means for serial-to-parallel converting row data of said one cell block in response to said first serial selection control signal;
• second serial-to-parallel converting means for serial-to-parallel converting row data of said another cell block in response to said second serial selection control signal;
• input/output buffering means for alternately selecting said serial converted serial data pairs in response to said serial input/output serial selection control signal;
• and
• control signal generating means for generating said row and column address signals, row and column clocks and an internal control signal by receiving external row and column address strobe signals, external row and column clocks, and an external control signal.