Integrated circuit memory with disabled edge transition pulse generation during special test mode

An integrated memory circuit, having a normal operating mode and a special test mode, comprising:

• a plurality of memory cells, arranged in rows and columns;
• a plurality of address terminals, for receiving an address signal;
• a plurality of data terminals;
• a control terminal;
• circuitry for selecting one of said plurality of memory cells responsive to the address signal received at said plurality of address terminals;
• edge transition detection circuitry, coupled to said plurality of address terminals and to said plurality of data terminals, for initiating a memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or data terminals;
• and
• test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal;
• wherein said edge transition detection circuitry is coupled to said test mode enable circuitry to receive the test mode enable signal, so that said edge transition detection circuitry is inhibited from initiating the memory operation responsive to said test mode enable signal.

A method of operating an integrated circuit that includes a memory having a normal operating mode and a special test mode, comprising the steps of:

• monitoring a plurality of input terminals to detect a logic level transition thereat;
• responsive to detecting a logic level transition at one of the plurality of input terminals, initiating a memory operation;
• receiving a test mode select signal;
• responsive to receiving the test mode select signal, initiating the special test mode for the memory;
• and
• responsive to receiving the test mode select signal, inhibiting the initiation of the memory operation responsive to detecting the logic level transition at one of the plurality of input terminals.

A method of operating an integrated circuit that includes a memory having a normal operating mode and a special test mode, comprising the steps of:

• monitoring a plurality of address terminals and data terminals to detect a logic level transition thereat;
• responsive to detecting a logic level transition at one of the plurality of address terminals or data terminals, initiating a memory operation;
• receiving a test mode select signal;
• responsive to receiving the test mode select signal, initiating the special test mode for the memory;
• and
• responsive to receiving the test mode select signal, inhibiting the initiation of the memory operation responsive to detecting a logic level transition at one of the plurality of address and data terminals.