Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device

Apparatus for providing the number of redundancy memory cells selected to replace defective memory cells in a memory matrix that has at least one sector and is in communication with an output data bus and an address bus having cell and sector address portions, comprising;

• a first redundancy address cell associated with a first one of said redundancy memory cells and operable to store a default address until programmed with an address of a first defective memory cell in a first sector of said matrix having a first sector address;
• a first selection circuit operable to generate a first redundancy select signal when the address stored in said first redundancy address cell occupies said cell address portion of said address bus;
• a control circuit operable to generate a check-number signal during a check-number mode;
• and
• a multiplexer operable to couple said redundancy select signal to said output data bus in response to said check-number signal.

Method for providing the number of redundancy memory cells selected to replace defective memory cells in a memory matrix that has at least one sector and is in communication with an output data bus and an address bus having cell and sector address portions, comprising;

• storing a default address in a first redundancy address cell associated with a first one of said redundancy memory cells until said address cell is programmed with an address of a first defective memory cell in a first sector of said matrix having a first sector address;
• generating a first redundancy select signal when the address in said first redundancy address cell occupies said cell address portion of said address bus;
• generating a check-number signal to indicate a check-number mode;
• and
• coupling said redundancy select signal to said output data bus during said check-number mode.

A memory circuit comprising:

• an address bus;
• an output data bus;
• a memory matrix having at least one sector of memory cells and redundancy memory cells operable to replace defective ones of said memory cells;
• redundancy address cells each associated with one of said redundancy memory cells and operable to store a default address until programmed with an address of a first defective memory cell:
• selection circuits each operable to generate a redundancy selection signal when the address stored in an associated one of said redundancy address cells occupies said address bus;
• a control circuit operable to generate a check number signal during a check number mode of the memory circuit;
• and
• a multiplexer operable to receive said check number signal and to couple said redundancy selection signals to said output data bus during said check number mode, and to couple a selected memory or redundancy memory cell from said memory matrix to said output data bus during an operational mode of the memory circuit.