Method and apparatus for enhanced EPROM and EEPROM programmability and process scaling
AssigneeAltera Corporation
InventorsJohn E. Turner, Myron W. Wong
Life of this patent
Estimating the term…
Abstract
An EPROM or EEPROM employs an alternate voltage level of 2 volts replaces solid ground (0 volts) during programming and performs a `zero` logic level function. This `soft` zero of 2 volts is applied to bit lines not selected for programming. As a soft zero, this alternative voltage reduces internal voltage stresses and helps prevent field inversion and keep parasitic field transistors between bit lines shut off. By reducing internal voltage stresses on gate oxides, and by helping prevent field inversion, the use of a soft zero voltage allows smaller circuit architectures to be designed for a given high programming voltage.
Claims15
An integrated circuit device having memory cells programmed at a high programming voltage higher than operating voltage, said device comprising:
- a) a plurality of memory cell transistors sharing a word line, said memory transistors having sources and drains coupled to doped column regions said doped column regions being separated by a nonconducting region;
- b) program selecting means for selecting a first group of said memory transistors for programming, said program selecting means including means for coupling diffused drains of said first group of memory transistors to said high programming voltage for a period of time;
- and
- c) means for selecting a second group of said plurality of memory transistors for program voltage protection, at least some of said second group of memory transistors adjacent said first group of memory transistors, wherein said second group of memory transistors are not selected for programming, said means for selecting a second group including means for coupling diffused column regions of said second group of memory transistors to an alternate programming voltage below said operating voltage and above ground level during said period of time.
A method of programming memory cells programmed at a high programming voltage higher than operating voltage, said method comprising the steps of:
- a) selecting a memory cell transistor for programming;
- b) applying said programming voltage via a first control line to one electrode of said selected memory cell transistor;
- and
- c) applying an alternate programming voltage via a control line not connected to said selected memory cell to an electrode of a transistor adjacent to said selected memory cell transistor, wherein said alternate voltage is below said operating voltage and above ground level.
A method of programming memory cells programmed at a high programming voltage higher than operating voltage, said method comprising the steps of:
- a) selecting a memory cell transistor for programming comprising selecting at least one memory transistor of a plurality of memory transistors sharing a word line;
- b) applying said programming voltage to one electrode of said selected memory cell transistor;
- and
- c) applying an alternate programming voltage to an electrode of a transistor adjacent to said selected memory cell transistor, wherein said alternate voltage is below said operating voltage and above ground level comprising applying said alternate programming voltage to sources and drains of any of said plurality of memory transistors not selected for programming wherein said memory cells are dual bit line memory cells having a write bit line and a read bit line, and wherein said step of applying said alternate voltage comprises applying said alternate programming voltage only to substantially all read lines of said plurality of memory cells.
A method of programming memory cells programmed at a high programming voltage higher than operating voltage, said memory cells arranged in an array connected in one direction by a plurality of word-lines and in another direction by a plurality of bit-lines, said method comprising the steps of:
- a) selecting a memory cell transistor for programming by applying a programming voltage to a bit-line and word-line connected to said memory cell;
- and
- b) applying an alternate programming voltage to bit-lines adjacent to the bit-line of said selected memory cell wherein said alternate voltage is below said operating voltage and above ground level.
Dependencies are inferred from the claim text.