Carry-chain compiler
AssigneeVLSI Technology, Inc.
InventorsLin Yang, Chun-Ling Liu
Life of this patent
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Abstract
Carry-chain structures useful in circuits such as adders, subtractors, counters and arithmetic logic units (i.e., ALU's). The carry-chain structures have regular architectures that can be conveniently generated in various bit widths by automated compiler systems. In a preferred embodiment, a method for automatically generating a carry-chain circuit using a compiler which includes a library of cells by selecting a first cell from the library of cells for use as a carry propagation cell, and using the first cell for multiplexing a carry signal produced by the carry propagation cell, such that the carry-chain includes a plurality of first cells. Further, a carry-chain architecture is produced using the aforementioned method.
Claims18
A carry-chain architecture comprising;
- a first stage having a first cell for effecting carry signal propagation of a first provisional carry signal and a second provisional carry signal and at least one multiplexer cell for effecting carry signal multiplexing to select one of said first provisional carry signal and said second provisional carry signal as a first carry-out signal, said first carry-out signal being input to at least two additional multiplexer cells to select carry-out signals of additional stages, the number of carry-out signals selected by said first carry-out signal being greater than a number of carry-out signals selected by a carry-out signal of a preceding stage in the carry chain architecture;
- at least one of said additional stages having a first cell for effecting carry signal propagation of a provisional carry signal and said at least two additional multiplexer cells for effecting carry signal multiplexing to produce a second carry-out signal in response to said first carry-out signal, each of said first cells and said multiplexer cells including:
- an input circuit for receiving a carry-in signal;
- a pull-down circuit for receiving a first control signal;
- a pull-up circuit for receiving a second control signal;
- and
- an output node for producing an output signal in response to said carry-in signal, said pull-down circuit and said pull-up circuit.
A carry-chain architecture having plural stages which each include a carry signal multiplexer cell for use in an integrated circuit, each carry-signal multiplexer cell comprising:
- an input circuit for receiving a carry-in signal;
- a pull-down circuit for receiving a first control signal;
- a pull-up circuit for receiving a second control signal, said pull-up circuit including an inverter for inverting the second control signal;
- and
- an output node for producing a first carry-out signal selected in response to said carry-in signal, said pull-down circuit and said pull-up circuit, said first carry-out signal being input to at least two additional carry signal multiplexer cells to select carry-out signals of additional stages, the number of carry-out signals selected by said first carry-out signal being greater than a number of carry-out signals selected by a carry-out signal of a preceding stage in the carry chain architecture.
A carry-chain architecture comprising:
- a first stage having a first cell for generating at least two provisional carry-out signals and a second cell for selecting one of said at least two provisional carry-out signals as a first carry-out signal, said first carry-out signal being input to at least two additional multiplexer cells to select carry-out signals of additional stages, the number of carry-out signals selected by said first carry-out signal being greater than a number of carry-out signals selected by a carry-out signal of a preceding stage in the carry chain architecture;
- and
- at least one of said additional stages having a first cell for generating at least two provisional carry-out signals, and having a second cell for selecting one of said at least two provisional carry-out signals of said at least one additional stage as a second carry-out signal in response to said first carry-out signal, said first and second cells being configured such that there is at most a single unit delay between generation of said first carry-out signal and said second carry-out signal.
Dependencies are inferred from the claim text.