US 5,493,520 AGranted

Two state leading zero/one anticipator (LZA)

AssigneeInternational Business Machines Corporation

InventorsMartin S. Schmookler, Donald G. Mikan, Jr.

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Abstract

An apparatus and method for anticipating leading zeros/ones used in normalizing the results of a full adder. The propagate (P), generate (G) and zero (Z) states of the two inputs to the adder are combined in two stages of logic to derive a pair of state outputs L.phi.S and L1S which fully specify by respective bit strings the leading zero and leading one conditions of the output from the adder. The two state bit strings, one representing the leading zero evaluation and the second representing the leading one evaluation, are then compared to determine which one of the two is applicable, correspondingly indicating whether the adder result is a positive or a negative value, and the number of leading bit positions requiring shifted removal during the normalization process. The leading 0/1 anticipator according to the present invention lends itself to high speed and low device count circuit implementations.

Claims16

Dependent claims

A leading digit anticipator apparatus utilized in conjunction with an adder of a digital processor, said adder receiving as inputs first and second data bit streams, comprising:

means for logically combining said first and said second data bit strings to derive P, Z, and G bit strings, wherein each bit position within said P bit string is derived by XORing corresponding bit positions of said first and second data bit strings, and wherein each bit position within said Z bit string is derived by ORing corresponding bit positions of said first and second data bit strings, and wherein each bit position within said G bit string is derived by ANDing corresponding bit positions within said first and second data bit strings;
means for logically combining said P and Z bit strings to derive a PZ bit string and for logically combining said P and G bit strings to derive a PG bit string;
means for determining from said PZ bit string a possible number of leading zeros within a sum of said first and second data bit strings;
and
means for determining from said PG bit string a possible number of leading ones within a sum of said first and second data bit strings, wherein a number of leading zeros or ones within a sum is efficiently determined.

2 more elements

A method within a digital processor for anticipating leading digits within a sum of an adder, said adder receiving as inputs first and second data bit strings, said method comprising:

logically combining said first and said second data bit strings to derive P, Z, and G bit strings, wherein each bit position within said P bit string is derived by XORing corresponding bit positions of said first and second data bit strings, and wherein each bit position within said Z bit string is derived by ORing corresponding bit positions of said first and second data bit strings, and wherein each bit position within said G bit string is derived by ANDing corresponding bit positions within said first and second data bit strings;
logically combining said P and Z bit strings to derive a PZ bit string;
logically combining said P and G bit strings to derive a PG bit string;
determining from said PZ bit string a possible number of leading zeros within a sum of said first and second data bit strings;
and
determining from said PG bit string a possible number of leading ones within a sum of said first and second data bit strings, wherein a number of leading zeros or ones within a sum is efficiently determined.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/228,323Filed 15 Apr 1994
Granted: 20 Feb 1996
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 7/74
Methods or arrangements for processing data by operating upon the order or content of the data handled: selecting or encoding within a word the…
G06F 7/485
Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or…:…
G06F 7/49936
Denomination or exception handling, e.g. rounding or overflow: normalisation mentioned as feature only
G06F
Computing and data processing