Method of and apparatus for generating mask layouts

A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of:

• reading graphic data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles;
• cutting the data in said second memory device along said first cutting lines to produce a plurality of first segment data items;
• compacting these first segment data items in the direction of the second cutting line;
• cutting these compacted first segment data items along the second cutting lines to produce a plurality of second segment data items;
• compacting these second segment data items in the direction of the first cutting line;
• and
• connecting these compacted second segment data items to each other and storing the resulting data in said first memory device.

An apparatus for generating mask layouts for semiconductor integrated circuits, comprising:

• first memory means for storing data representing a symbolic layout for a semiconductor integrated circuit, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles;
• first generating means for reading said data from said first memory means and cutting the data along said first cutting lines to produce a plurality of first segment data items;
• first compacting means for compacting said first segment data in the direction of the second cutting line;
• first connecting means for connecting the first segment data items compacted by said compacting means according to the first cutting lines;
• second generating means for cutting the connected first segment data along the second cutting lines to produce a plurality of second segment data items;
• second compacting means for compacting said second segment data items in the direction of the first cutting line;
• and
• second connecting means for connecting the second segment data items compacted by said second compacting means.

A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of:

• reading data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles;
• cutting the data read from said second memory device along said first cutting lines to produce a plurality of first segment data items, each of said first segment data items being partitioned from each other;
• compacting these first segment data items in a direction of the second cutting lines;
• connecting these compacted first segment data items according to the first cutting lines;
• cutting the entire first segment data thus connected along the second cutting lines to produce a plurality of second segment data items, each of said second segment data items being partitioned from each other;
• compacting these second segment data items in a direction of the first cutting lines;
• and
• connecting these compacted second segment data items to each other and storing resulting data in said first memory device.