Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising:

• a first step of generating each of functional models from each of a plurality of previously divided circuit units;
• a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language;
• a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them;
• a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models;
• and
• a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware units for controlling said digital circuit as a unit, said method comprising:

• a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface;
• a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language;
• a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them;
• a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state;
• and
• a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising:

• a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language;
• a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed;
• and
• a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.

A digital circuit design assist system for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said system comprising:

• a functional model storage unit for storing each functional model functionally expressing each of said hardware units by a hardware description language through a text editor by coding input;
• a logic synthesis means for converting said functional model into a structural model structurally expressed by said hardware description language;
• a structural model storage unit for storing said structural model;
• a language model library storage unit for storing a language model expressing each of a plurality of components constituting each of said hardware units by said hardware description language;
• and
• a hardware description language simulation means for verifying whether or not the logic of each said hardware unit is correct with regard to said functional model, said structural model and said language model, via a test model which supplies a test pattern to each of said functional models and each of said structural models and receives outputs from the models to verify the behaviors of the models.

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising:

• a first step of generating each of functional models from each of a plurality of previously divided circuit units;
• a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language;
• a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them;
• a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models;
• and
• a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising:

• a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface;
• a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language;
• a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them;
• a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state;
• and
• a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising:

• a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language;
• a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed;
• and
• a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.