Amplifier including circuit for reducing input capacitance
AssigneeNational Semiconductor Corporation
InventorAlexander Fairgrieve
Life of this patent
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Abstract
The input capacitance of a differential amplifier is reduced by connecting a positive feedback path between the collector of each input transistor and a terminal of a resistor connected in the other parallel current path. The positive feedback paths cause the voltage at the collector of each input transistor to move in the same direction as the voltage at the base of that input transistor, and thereby reduce the effective input capacitance seen at the input terminals of the differential amplifier.
Claims12
A differential amplifier comprising:
- a first current path including a first input transistor, a first cascode transistor and a first resistor, said first resistor being connected between said first cascode transistor and said first input transistor;
- a second current path including a second input transistor, a second cascode transistor and a second resistor, said second resistor being connected between said second cascode transistor and said second input transistor;
- a first feedback path extending between a terminal of said first resistor and a collector terminal of said second input transistor;
- and
- a second feedback path extending between a terminal of said second resistor and a collector terminal of said first input transistor.
A differential amplifier comprising:
- a first current path including a first input transistor, a first cascode transistor, a first load element and a first resistor, said first load element being connected between said first resistor and said first cascode transistor;
- a second current path including a second input transistor, a second cascode transistor, a second load element and a second resistor, said second load element being connected between said second resistor and said second cascode transistor;
- a first feedback path extending between a terminal of said first resistor and a collector terminal of said second input transistor;
- and
- a second feedback path extending between a terminal of said second resistor and a collector terminal of said first input transistor.
A differential amplifier comprising:
- a first current path, said first current path comprising a first input transistor, a first emitter-follower transistor, a first load element and a first resistor, said first load element being connected between said first resistor and said first emitter-follower transistor;
- a second current path, said second current path comprising a second input transistor, a second emitter-follower transistor, a second load element and a second resistor, said second load element being connected between said second resistor and said second emitter-follower transistor;
- a first feedback path extending between a terminal of said first resistor and a base terminal of said second emitter-follower transistor, said first feedback path equalizing the voltage at said terminal of said first resistor and said base terminal of said second emitter-follower transistor;
- and
- a second feedback path extending between a terminal of said second resistor and a base terminal of said first emitter-follower transistor, said second feedback path equalizing the voltage at said terminal of said second resistor and said base terminal of said first emitter-follower transistor.
A differential amplifier comprising:
- a first current path including a first input transistor, said first input transistor having a base terminal for receiving a first differential input voltage;
- a second current path including a second input transistor, said second input transistor having a base terminal for receiving a second differential input voltage;
- a first feedback path extending between a first node and a collector terminal of said first input transistor;
- and
- a second feedback path extending between a second node and a collector terminal of said second input transistor;
- wherein said amplifier is configured such that a voltage at said first node and a voltage at said collector terminal of said first input transistor increase when said first differential input voltage increases relative to said second differential input voltage and decrease when said first differential input voltage decreases relative to said second differential input voltage and such that a voltage at said second node and a voltage at said collector terminal of said second input transistor increase when said second differential input voltage increases relative to said first differential input voltage and decrease when said second differential input voltage decreases relative to said first differential input voltage.
A method of reducing the input capacitance of a differential amplifier, said differential amplifier comprising first and second input transistors, a first differential input voltage being applied to a base terminal of said first input transistor and a second differential input voltage being applied to a base terminal of said second input transistor, said method comprising causing a voltage at a collector terminal of said first input transistor to move in the same direction as said first differential input voltage and causing a voltage at a collector terminal of said second input transistor to move in the same direction as said second differential input voltage.
Dependencies are inferred from the claim text.