Breakdown protection circuit using high voltage detection

A high voltage circuit comprising:

• first switching means for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) greater than ground potential;
• a first p-channel transistor having a drain and a gate and having a source connected to said first switching means;
• a second p-channel transistor having a drain and a gate and having a source connected to said drain of said first p-channel transistor;
• control signal means for selectively switching said gate of said first p-channel transistor between a positive voltage and ground potential to turn said first p-channel transistor off and on, respectively;
• second switching means responsive to said first switching means and connected to said gate of said second p-channel transistor for applying V.sub.cc when said first switching means supplies V.sub.pp and for applying ground potential when said first switching means supplies V.sub.cc.

A high voltage inverter circuit comprising:

• a signal input;
• a signal output to be switched between 0 volts and a positive voltage level (V.sub.cc) and between 0 volts and a boosted positive voltage level (V.sub.pp) in response to said signal input;
• voltage supply means having a first node for selectively switching the potential at said first node between V.sub.cc and V.sub.pp ;
• a first controlled path coupled between said first node and said signal output, said first controlled path including first and second p-channel transistors connected in series, with a source of said first p-channel transistor connected to said voltage supply means and with a drain of said second p-channel transistor connected to said signal output, each of said first and second p-channel transistors having a gate;
• detection means coupled to said voltage supply means for supplying ground potential to said gate of said second p-channel transistor when said first node is at V.sub.cc and supplying V.sub.cc to said gate of said second p-channel transistor when said first node is at V.sub.pp ;
• a second controlled path from said signal output to ground potential, said second controlled path including first and second n-channel transistors connected in series, with a drain of said first n-channel transistor connected to said signal output and with a source of said second n-channel transistor connected to ground potential, said first n-channel transistor having a gate connected to receive a fixed V.sub.cc ;
• and
• switching means having an input connected to said signal input and having an output connected to gates of said first p-channel and second n-channel transistors for supplying a positive voltage to said gates when said signal input is at a logic high and for supplying ground potential when said signal input is at a logic low, said positive voltage being sufficient to turn said first p-channel transistor to an off state;
• wherein when said first node is at V.sub.pp and said switching means supplies said positive voltage to said gate, the voltage at the drain of said first p-channel transistor is maintained substantially at the voltage of the gate of said second p-channel transistor minus the threshold voltage of said second p-channel transistor.