Status register with asynchronous read and reset and method for providing same

A status register comprising:

• (a) a plurality of register sections, each of which includes:
• (i) an input flip-flop having an input coupled to a status input and having an output, said input flip-flop being clocked by a clocking signal derived from a system clock;
• (ii) an asynchronous latch having an input coupled to said output of said input flip-flop and having an output, where said asynchronous latch is enabled by a read status signal for reading said output of said latch asynchronously with respect to said system clock;
• (iii) a register section comparison mechanism coupled to said output of said input flip-flop and said output of said asynchronous latch and operative to produce a comparison output for said register section;
• (b) a collecting mechanism for collecting the comparison outputs of each of the plurality of register sections and producing a collective comparison output;
• and
• (c) an output stage which does not include a latch and which is coupled to said collective comparison output for providing an error output when said output of said input flip-flop and said output of said latch for at least one of said plurality of register sections are different, wherein said output stage is coupled to said outputs of said asynchronous latch, of each of said register sections and is operative to provide a status register output when said output of said input flip-flop and said output of said asynchronous latch for each of said plurality of register sections is the same.

A method for providing a status output comprising the steps of:

• capturing a status bit in an input flip-flop;
• latching said status bit into an output latch;
• asynchronously enabling said output latch by means of a read status signal for reading an output of said output latch;
• comparing an output of said input flip-flop against said output of said output latch;
• outputting an error signal if said output of said input flip-flop and said output of said output latch are different;
• outputting said status bit at least if said output of said input flip-flop and said output of said output latch are the same;
• and
• disabling a reset of said input flip-flop if said output of said input flip-flop and said output of said output latch are different.

A status register comprising:

• an input flip-flop having an input coupled to a status input, and also having an output and a reset input, said input flip-flop being clocked by a clocking signal derived from a system clock;
• an asynchronous latch having an input coupled to said output of said input flip-flop and having an output, where said asynchronous latch is enabled by a read status signal for reading said output of said latch asynchronously with respect to said system clock;
• a comparator coupled to said output of said input flip-flop and said output of said asynchronous latch and operative to produce a comparison output;
• an output stage coupled to said comparison output to provide an error output when said output of said input flip-flop and said output of said asynchronous latch are different;
• and
• a reset disabling mechanism coupled between said comparison output and said reset input of said input flip-flop and operative to prevent said input flip-flop from resetting when said output of said input flip-flop and said output of said asynchronous latch are different.