Memory having a decoder with improved address hold time

Abstract

A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation. The circuitry includes a delay circuit for delaying the select signal, a select circuit for selecting one of the select signal and the delayed select signal to be applied to the memory array, and a resettable delay circuit for delaying a memory operation control signal for a second predetermined delay time to select one of the select signal and the delayed select signal.

Dependencies are inferred from the claim text.