Circuit and method of configuring a field programmable gate array
AssigneeMotorola, Inc.
InventorFredrick Zlotnick
Life of this patent
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Abstract
A field programmable gate array (FPGA) configuration circuit reads configuration data from a memory (12) and converts the parallel data to a serial data stream through a shift register (16) clocked by a clock signal. A first FPGA (18) controls the serial data stream by providing the clock signal when enabled by a start signal. Once the configuration data has been completely loaded into the first FPGA, the first FPGA outputs a done signal to a second FPGA (20) to enable it's clock to control the serial data stream into the second FPGA. The clock from the first FPGA is disabled. Each FPGA passes control to the next FPGA in a daisy chain arrangement by enabling the clock source from the next FPGA while disabling the clock source from previous FPGA as each finishes loading its configuration data.
Claims19
A circuit for configuring a plurality of field programmable gate arrays (FPGA), comprising:
- a first memory providing a data word at an output in response to an address signal;
- a first shift register having a data input, a clock input and a serial output, said data input being coupled for receiving said data word, said clock input being coupled for receiving a clock signal;
- a first FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled for receiving a start signal, said clock output providing said clock signal to said first shift register when enabled by said start signal, said done output providing a logic signal indicating completion of loading configuration data into said first FPGA;
- and
- a second FPGA having a data input, an enable input, a done output, and a clock output, said data input being coupled to said serial output of said first shift register, said enable input being coupled to said done output of said first FPGA, said clock output providing said clock signal to said first shift register when enabled by said logic signal from said done output of said first FPGA.
A field programmable gate array (FPGA) configuration circuit, comprising:
- a first memory providing a data word at an output in response to an address signal;
- a first shift register having a data input, a clock input and a serial output, said data input being coupled for receiving said data word, said clock input being coupled for receiving a clock signal;
- and
- a plurality of FPGAs each having a data input, an enable input, a done output, and a clock output, where said data input of a first FPGA is coupled to said serial output of said first shift register, and said enable input of said first FPGA is coupled for receiving a start signal, and said clock output of said first FPGA provides said clock signal to said first shift register when enabled by said start signal, and said done output of said first FPGA provides a logic signal indicating completion of loading configuration data into said first FPGA, and where said data input of a second FPGA is coupled to said serial output of said first shift register, and said enable input of said second FPGA is coupled to said done output of said first FPGA, and said clock output of said second FPGA provides said clock signal to said first shift register when enabled by said logic signal from said done output of said first FPGA.
A method of configuring a plurality of field programmable gate arrays (FPGA), comprising the steps of:
- retrieving a data word from a memory storage location specified by an address signal;
- converting said data word into a serial data stream in response to a clock signal;
- enabling a first oscillator signal in a first FPGA to act as said clock signal upon receiving start signal;
- disabling a second oscillator signal in a second FPGA;
- storing said serial data stream into a memory storage location of said first FPGA in response to said clock signal from said first FPGA;
- generating a done signal when said first FPGA is loaded with configuration data from said serial data stream;
- disabling said first oscillator signal in said first FPGA;
- enabling said second oscillator signal in said second FPGA to act as said clock signal upon activating said done signal from said first FPGA;
- and
- storing said serial data stream into a memory storage location of said second FPGA in response to said clock signal from said second FPGA.
Dependencies are inferred from the claim text.