Programmable and stable threshold CMOS inverter

An inverter circuit for inverting an input voltage to provide an output voltage, said inverter circuit comprising:

• a current mirror having a first current path through which a first current flows and a second current path through which a second current flows, said second current being proportional to said first current, wherein said first current path has a bias voltage terminal adapted to receive a bias voltage and an input voltage terminal adapted to receive said input voltage, and wherein said first and second currents are a function of said bias voltage;
• an output stage comprising a first transistor having a gate terminal coupled to said second current path and a second transistor having a gate terminal receiving said input voltage, said first and second transistors being interconnected at said output terminal of said inverter;
• and
• a third transistor disposed in said first current path and having a gate terminal providing said bias voltage terminal and a fourth transistor disposed in said first current path and having a gate terminal providing said input voltage terminal, said third and fourth transistors coupled in series at an interconnection node, said inverter further comprising a fifth transistor disposed in said output current path of said current mirror, said fifth transistor having a gate terminal coupled to said interconnection node.

An inverter for inverting an input voltage to an output voltage at an output terminal having an opposite logic state with respect to said input voltage, said inverter comprising:

• a first transistor having a drain terminal, a gate terminal receiving an input voltage, and a source terminal;
• a second transistor having a drain terminal, a gate terminal connected to said drain terminal of said first transistor and a source terminal;
• a third transistor having a drain terminal, a gate terminal receiving a bias voltage, and a source terminal connected to said drain terminal of said first transistor;
• a current mirror comprising:
• an input transistor having a drain terminal connected to said drain terminal of said bias transistor, a gate terminal, and a source terminal;
• and
• an output transistor having a drain terminal connected to said drain terminal of said second transistor, a gate terminal connected to said gate terminal of said input transistor, and a source terminal;
• an output PMOS transistor having a drain terminal at which said output voltage is provided, a gate terminal, and a source terminal connected to a supply voltage;
• and
• an output NMOS transistor having a drain terminal connected to said drain terminal of said output PMOS transistor, a gate terminal, and a source terminal connected to ground.

An inverter circuit for inverting an input voltage to provide an output voltage having an opposite logic state with respect to said input voltage, said inverter circuit comprising:

• an input stage comprising a pair of transistors, a first one of said pair of transistors being disposed in a first current path between a supply voltage and ground and the second one of said pair of transistors being disposed in a second current path between said supply voltage and ground, wherein said first transistor is adapted to receive said input voltage, said input stage further comprising a bias transistor disposed in said first current path for receiving a bias voltage, said pair of transistors and said bias transistor being of the same type, either NMOS and PMOS;
• an output stage comprising a PMOS transistor and an NMOS transistor having interconnected drain terminals at which said output voltage is provided, wherein said output voltage logic state transitions when said input voltage is at a predetermined threshold voltage;
• and
• a current mirror having an input transistor in said first current path and an output transistor in said second current path, said input and output transistors of said current mirror having interconnected gate terminals.