Electrically erasable PROM (E.sup.2 PROM) with thin film peripheral transistor

An Electrically Erasable PROM (E.sup.2 PROM) in which a negative bias method is used for a erasure operation, the E.sup.2 PROM comprising:

• a semiconductor substrate of a first conductivity type having a field oxide formed on a predetermined region of a main surface;
• a memory section formed on the semiconductor substrate, the memory section including a plurality of second channel type non-volatile transistors formed on the semiconductor substrate, each of the nonvolatile transistors having a floating gate and a control gate;
• and
• a peripheral circuit section formed in the peripheral of the memory section,
• wherein the peripheral circuit section has a CMOS structure in which a first channel type MOS transistor and a second channel type MOS transistor are connected to each other in a complementary manner;
• and
• wherein the second channel MOS transistor is a thin film transistor formed on the field oxide and the first channel MOS transistor is a MOS transistor formed on the semiconductor substrate.