Method of making structure for suppression of field inversion caused by charge build-up in the dielectric
AssigneeVLSI Technology, Inc.
InventorsSubhash R. Nariani, Vivek Jain, Dipankar Pramanik, Kuang-Yeh Chang
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Abstract
The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
Claims17
A method of making an integrated circuit comprising the steps of:
- forming at least two electrical devices on a substrate;
- forming an isolation means between said at least two electrical devices for electrically isolating the electrical devices;
- forming a first dielectric layer on said isolation means;
- forming a metallization layer on said dielectric layer;
- forming a second dielectric layer on said metallization layer;
- and
- forming a first layer of amorphous silicon beneath at least one of said first dielectric layer and said second dielectric layer.
A method of making an integrated circuit comprising the steps of:
- forming at least two electrical devices on a substrate;
- forming an isolation means between said at least two electrical devices for electrically isolating the electrical devices;
- forming a first dielectric layer on said isolation means;
- forming a conductive layer on said first dielectric layer;
- forming a second dielectric layer on said conductive layer;
- forming a first layer of amorphous silicon on a first side of at least one of said first dielectric layer and said second dielectric layer;
- and
- forming another layer of amorphous silicon on a second side of said at least one dielectric layer which is opposite said first side.
A method of making an integrated circuit comprising the steps of:
- forming at least two electrical devices on a substrate;
- forming an isolation means between said at least two electrical devices for electrically isolating the electrical devices;
- forming a first dielectric layer on said isolation means;
- forming a conductive layer on said first dielectric layer;
- forming a second dielectric layer on said conductive layer;
- forming a layer of amorphous silicon on a first side of at least one of said first dielectric layer and said second dielectric layer;
- and
- forming an intermetal oxide sandwich which includes upper and lower oxide layers, at least one of said first and second dielectric layers being a spin-on-glass layer located between said upper and lower oxide layers.
A method of making an integrated circuit comprising the steps of:
- forming at least two electrical devices on a substrate;
- forming an isolation means between said at least two electrical devices for electrically isolating the electrical devices;
- forming a first dielectric layer on said isolation means;
- forming a conductive layer on said first dielectric layer;
- forming a second dielectric layer on said conductive layer;
- and
- forming a first layer of amorphous silicon on a first side of at least one of said first dielectric layer and said second dielectric layer, wherein at least one of said first and second dielectric layers is a BPSG layer formed on said isolation means between said isolation means and said conductive layer.
Dependencies are inferred from the claim text.