A method for enhanced instruction dispatch efficiency in a superscalar processor system capable of simultaneously dispatching multiple scalar instructions from a dispatch buffer to a plurality of execution units during a single cycle, each of said multiple scalar instructions including at least one source operand and one destination operand, wherein results of execution of said multiple scalar instructions are stored in a plurality of general purpose registers, said method comprising the steps of:
- assigning a particular one of a plurality of intermediate storage buffers to a destination operand within each one of said multiple scalar instructions;
- storing a relationship between each one of said plurality of intermediate storage buffers and a designated one of said plurality of general purpose registers in a storage buffer index;
- temporarily storing results of execution of each one of said multiple scalar instructions in an assigned one of said plurality of intermediate storage buffers;
- and
- transferring said results of execution from a particular one of said plurality of intermediate storage buffers to an alternate one of said plurality of execution units for utilization in execution of an alternate one of said multiple scalar instructions utilizing said storage buffer index prior to a transfer of said results of execution from said particular one of said plurality of intermediate storage buffers to said designated one of said plurality of general purpose registers.