Power-on sequencing apparatus for initializing and testing a system processing unit

Power on sequence apparatus for use with a processing unit which couples to a system bus and issues commands to any one of a plurality of units coupled in common with said processing unit for performing data processing operations, said processing unit including a microprocessor coupled to a synchronous local bus for issuing said commands to said system bus, said apparatus comprising:

• an electrically erasable programmable read only memory (EEPROM) unit including at least first and second groups of addressable locations, each first and second groups including a starting location normally referenced by said microprocessor for executing a boot-up routine sequence when said processing unit is powered on and placed in an initial state,
• said first group of locations assigned an address space addressable by said microprocessor when in said initial state, said first group of locations storing routines of on-board diagnostic (OBD) routines for testing said processing unit;
• and,
• said second group of addressable locations having the same address space addressable by said microprocessor when in said initial state for storing said boot-up routine sequence;
• and,
• control circuit means coupled to said EEPROM unit and to said system bus, said control circuit means including programmable array logic (PAL) circuit means coupled to said system bus for receiving control and command signals, said PAL including mode indicator means having a plurality of states, said PAL circuit means switching said mode indicator means to a first state in response to a master clear signal from said system bus generated as part of a system initialization procedure when said processing unit is powered on, said mode indicator mean when in said first state supplying at least one signal for causing said EEPROM unit to allow said microprocessor to address only said first group of locations including said starting location, storing said OBD routines for enabling both initialization and testing of said processing unit to verify that said processing unit is operational and when said mode indicator means is switched from said first state to a second one of said plurality of states upon completing said testing for supplying a signal for causing said EEPROM unit to allow said microprocessor to address only said second group of locations including said starting location of said boot-up sequence without having to change normal microprocessor addressing for said boot-up routine sequence.