Fault tolerant digital computer system having two processors which periodically alternate as master and slave
AssigneeUnisys Corporation
InventorSeyed H. Hashemi
Life of this patent
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Abstract
In a multiprocessor system, at least one processor is acting as a master processor and another processor is acting as the slave or shadow processor that checks operation of the first processor. Periodically, a controller switches operating mode of a master or main processor to slave or shadow mode, and at the same time switches operation of a slave or shadow processor to main or master processing mode. The first processor is then used as a slave or shadow processor to check operation of the second processor.
Claims1
A method of operating a fault tolerant digital computer system of the type which includes first and second processors with each such processor having a) a standalone master operating mode and b) a slave mode for monitoring the other processor, said method comprising the steps of:
- running said system in one state for a predetermined time interval where said first processor is in said master mode and said second processor is in said slave mode;
- running said system in an opposite state for another predetermined time interval where said second processor is in said master mode and said first processor is in said slave mode;
- and,
- periodicly switching the operation of said system from said one state to said opposite state, and vice-versa, such that said first and second processors are in said master mode during respective time intervals which are interleaved.
Dependencies are inferred from the claim text.