Real-time implementation of a 8Kbps CELP coder on a DSP pair
AssigneeHughes Aircraft Company
InventorsPrabhat K. Gupta, Allan Lamkin, Walter R. Kepley, III
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Abstract
A codec uses low cost digital signal processors (DSPs) to implement the codebook excited linear prediction (CELP) algorithm. The flexible architecture provides a platform for implementing a family of CELP codecs. In a specific example, an 8 Kbps CELP codec is partitioned into parallel tasks for real time implementation on dual DSPs with flexible intertask communication, prioritization and synchronization with asynchronous transmit and receive frame timings. The two DSPs are used in a master-slave pair. Each DSP has its own local memory. The DSPs communicate to each other through interrupts. Messages are passed through a dual port RAM. Each dual port RAM has separate sections for command-response and for data.
Claims5
A codebook excited linear prediction (CELP) codec comprising a master processor receiving and generating CELP parameters and a slave processor receiving speech samples and outputting regenerated speech, said master and slave processors communicating via mutually connected interrupts and a dual port random access memory (RAM) connected between said master and slave processors for temporarily storing messages passed between said master and slave processors, said master and slave processors sharing a stochastic and adaptive code book search, said master processor performing encoding of speech processed by said slave processor and stored in said dual port RAM based on said code book search, and said slave processor performing input buffering and speech decoding based on the CELP parameters generated by said master processor and stored in said dual port RAM.
Dependencies are inferred from the claim text.