US 5,491,728 A · Cell resequencing system for a telecommunication network

Abstract

A cell resequencing system is provided for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted. The resequencing section includes cell switching networks (SN2) having inlets (I2l/I2n/I2N) coupled to inputs (S1l/S1n/S1N) and outlets (N2l/N2m/N2M). The cells are subjected to a first variable time delay. The cell resequencing system (C1l/C1n/C1N, CK1; R2l/R2m/R2M, CK2) includes latches (R2l/R2m/R2M) coupled between the outlets (N2l/N2m/N2M) and the outputs (S2l/S2m/S2M) to subject the cells to a second variable time delay chosen for each cell so the sum of the first and second variable time delay is substantially equal to a predetermined constant time value, which determines the size of the latches (R2l/R2m/R2M). The resequencing section (RS) has two inputs (S1l, S1n/S1N) each coupled to a distinct inlet (I2l/I2n/I2 N) via a distinct transmission link (TLl/TLn/TLN). The cells are subjected to at least a fixed transfer delay (TD) during their transfer from the input (S1l/S1n/S1N) to the outlet (N2l/N2m/N2M). The fixed transfer delay forms part of the first variable time delay. The minimum size of the latches (R2l/R2m/R2M) is determined by a difference between a predetermined constant time value and the fixed transfer delay (TD).

Claims18

Dependent claims

A cell resequencing system for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted, said resequencing section having at least one input (S1l/S1n/S1N) and at least one output (S2l/S2m/S2M) and including at least one cell switching network (SN2) having at least one inlet (I2l/I2n/I2N) coupled to said input and at least one outlet (N2l/N2m/N2M), the cells transmitted from said input to said outlet being subjected to a first variable time delay and said cell resequencing system (C1l/C1n/C1N, CK1;

R2l/R2m/R2M, CK2) including latching means (R2l/R2m/R2M) coupled between said outlet and said output so as to subject said cells to a second variable time delay which is so chosen that for each cell the sum of said first and second variable time delay is substantially equal to a predetermined constant time value, said predetermined constant time value determining the size of said latching means,
characterized in that said resequencing section (RS) has at least two of said inputs (S1l/S1n/S1N) each coupled to a distinct inlet (I2l/I2n/I2N) via a distinct transmission link (TLl/TLn/TLN), said inputs and said transmission links being arranged in a link group (LG),
that said cells are supplied at any one of said inputs of said link group and are subjected to at least a fixed transfer delay (TD) during their transfer from said input to said outlet (N2l/N2m/N2M), said fixed transfer delay forming part of said first variable time delay, and that the minimum size of said latching means (R2l/R2m/R2M is determined by the difference between said predetermined constant time value and said fixed transfer delay (TD).

A method for correlating in phase a first clock means (CK1) producing successive first time stamp values (tA1, tA2) with a second clock means (CK2) producing successive second time stamp values (tB), both said clock means forming part of a telecommunication network and being a interconnected by at least one transmission link (TLl/TLn/TLN;

LG), characterized in that said first clock means (CK1) sends a then produced first time stamp value (tA1) to said second clock means (CK2) via said transmission link (TLl/TLn/TLN) and that said second clock means, upon receipt of said first time stamp value, immediately returns a then produced second time stamp value (tB) to said first clock means, whereby a time stamp compensation value (TTC) is determined at the location (A) of said first clock means, said time stamp compensation value being substantially equal to the difference between said second and said first time stamp values and being function of both the phase shift between said first and second clock means and a fixed transfer delay (TD) which is equal to the minimum delay needed for transmitting a time stamp value between said clock means.

Dependencies are inferred from the claim text.

Cell resequencing system for a telecommunication network

Life of this patent

Cell resequencing system for a telecommunication network

Life of this patent

Abstract

Claims18