Timing signal generation circuit

Abstract

A timing generator which is capable of generating a timing signal with high resolution and accuracy which is not affected by the changes in temperature and power supply voltage or the self-generated heat of the circuit component. The timing signal generator can generate a timing signal which has a delay time combined with a large delay time which is greater than the clock signal period and a small delay time which is smaller than the clock signal period. The timing signal generator includes a plurality of variable delay devices serially connected one another, a phase comparator which compares a total delay time of the variable delay devices with a clock signal and generates a voltage signal indicative of the difference between the two, a feed back circuit that feeds back the voltage signal from the phase comparator to the variable delay devices to form a phase locked loop so that the total delay time in the variable delay devices is equal to the one period of the clock signal, a synchronous delay circuit for generating a large delay time which is proportional to the clock signal period, a selector circuit for selecting one combination of the large delay time from the synchronous delay circuit and a small delay time from one of the variable delay devices.

Dependencies are inferred from the claim text.