Sense amplifier with isolation to bit lines during sensing
AssigneeSilicon Engineering, Inc.
InventorP. Owen Sharp
Life of this patent
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Abstract
A sense amplifier for sensing data from a pair of complementary bit lines. A bistable circuit is coupled to the bit lines through a pair of transistors. During the beginning of a sensing cycle, the transistors conduct allowing the bistable circuit to begin sensing the data on the lines. However, before the sense amplifier reaches one of its two stable states, the pair transistors cease conducting and isolate the bistable circuit from the bit lines. In this manner, the load associated with the bit lines is removed from the bistable circuit allowing it to more quickly sense data.
Claims2
A sense amplifier for sensing complementary data signals from static memory cells on first and second lines comprising:
- a first and a second node, said first node being coupled to said first line through a first isolation device, said second node being coupled to said second line through a second isolation device;
- said first and second nodes being cross coupled nodes in a latch;
- timing means coupled to said first and second isolation devices for causing said devices to isolate said latch from said first and second lines once said complementary data signals have been coupled to said latch and said latch has been activated so as to reduce the load on said latch as said latch seeks one of its two stable states.
A sense amplifier for sensing data from a pair of complementary bit lines having complementary data comprising:
- a bistable circuit having two stable states;
- an isolation circuit including a pair of transistors for coupling the bistable circuit to sense the complementary data from the pair of bit lines;
- for causing the pair of transistors to first couple the bistable circuit to the bit lines at the beginning of a first period of time as the bistable circuit is activated, then at the end of the first period of time to isolate the bistable circuit from the bit lines by causing the pair of transistors to cease conduction, the first period of time being long enough to begin sensing data from the bit lines but short enough to prevent the bistable circuit from reaching one of its two stable states while the pair of transistors are conducting.
Dependencies are inferred from the claim text.