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US 5,491,666 AGranted
Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
AssigneeIntel Corporation
InventorJay Sturges
Life of this patent
Estimating the term…
Abstract
An integrated circuit including a plurality of individual boundary scan circuits each associated with a separate portion of the circuitry of the integrated circuit. The registers of the individual boundary scan circuits are joined to provide a series boundary scan register chain in which individual portions of the circuitry included within the integrated circuit may be individually manipulated.
Claims12
An embedded controller system comprising:
- a central processor;
- main memory coupled to said central processor;
- an integrated circuit, coupled to said central processor comprising:
- a plurality of core logic circuits comprising at least one input and at least one output for implementing at least one logic or storage function during normal circuit operation, said core logic circuits being configured on a single substrate of said integrated circuit, and at least one output of a first core logic circuit being coupled to an input of a second core logic circuit;
- a plurality of independent test devices located on said single substrate, each independent test device comprising a controller and a plurality of registers that corresponds to a core logic circuit to receive data in said registers for boundary scan testing of said corresponding core logic circuit during a test operation;
- and
- wherein independent operation of said test devices permit configuring said registers in said second core logic circuit in response to said output of said first core logic circuit during normal circuit operation of said first core logic circuit and during test operation of said second core logic circuit.
4 more elements
An integrated circuit comprising:
- a plurality of core logic circuits comprising at least one input and at least one output for implementing at least one logic or storage function during normal circuit operation, said core logic circuits being configured on a single substrate of said integrated circuit, and at least one output of a first core logic circuit being coupled to an input of a second core logic circuit;
- a plurality of independent test devices located on said single substrate, each independent test device comprising a controller and a plurality of registers that corresponds to a core logic circuit to receive data in said registers for boundary scan testing of said corresponding core logic circuit during a test operation;
- and
- wherein independent operation of said test devices permit configuring said registers in said second core logic circuit in response to said output of said first core logic circuit during normal circuit operation of said first core logic circuit and during test operation of said second core logic circuit.
1 more element
Dependencies are inferred from the claim text.