I.sub.DDQ -testable RAM
AssigneeU.S. Philips Corporation
InventorManoj Sachdev
Life of this patent
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Abstract
An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An I.sub.DDQ -test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits.
Claims12
Electronic circuitry with a memory having a plurality of memory cells functionally organized in rows and columns, characterized in that the circuitry comprises test circuitry for selectively operative to connect and access simultaneously and in parallel a selected number of at least two memory cells of at least a particular one of the columns to simultaneously test said memory cells, at least nondefective ones of said memory cells not having hot-electron injection or Fowler-Nordheim tunneling induced during testing.
Dependencies are inferred from the claim text.