Semiconductor static random access memory device having previously equalizable memory cells
AssigneeNEC Corporation
InventorMasato Motomura
Life of this patent
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Abstract
A semiconductor static random access memory device has a bi-stable memory cell for storing a data bit in the form of potential difference between two memory nodes, and an equalizing transistor is connected between the two memory nodes for equalizing the two memory nodes at a balance level between a high level and a low level before rewriting the data bit, thereby causing the bi-stable memory cell to swing the voltage levels at the two memory nodes by a half of the potential difference.
Claims7
A semiconductor static random access memory device selectively entering into a write-in phase and a read-out phase, comprising:
- a first bit line and a second bit line paired with each other for propagating a potential difference indicative of a data bit;
- a word line changed between an active level and an inactive level in both write-in and read-out phases;
- and
- a memory cell coupled to first and second sources of voltage level different in voltage level from each other, and having
- first and second memory nodes for storing said potential difference indicative of said data bit,
- a first switching means coupled between said first and second memory nodes and said first and second bit lines, respectively when said word line is changed to said active level,
- a second switching means coupled between said first and second memory nodes and said first and second sources of voltage level, and operative to selectively connect said first and second memory nodes to said first and second sources of voltage level depending upon a logic level of said data bit, and
- an equalizing means coupled between said first memory node and said second memory node and responsive to a balance control signal for equalizing a voltage level at said first memory node to a voltage level at said second memory node.
A semiconductor static random access memory device selectively entering a write-in phase and a read-out phase, comprising:
- a first bit line and a second bit line paired with each other for propagating a potential difference indicative of a data bit;
- a word line changed between an active level and an inactive level in both write-in and read-out phases;
- and
- a memory cell having
- a first series combination of a first switching transistor of a first channel,conductivity type, a first memory node and a second switching transistor of a second channel conductivity type opposite to said first channel conductivity type, said first series combination being connected between a first source of power voltage level and a common node, said first and second switching transistor having respective gate electrodes connected to a second memory node,
- a second series combination of a third switching transistor of said first channel conductivity type, and a fourth switching transistor of said second channel conductivity type connected between said first source of power voltage level and said common node, said third and fourth switching transistor having respective gate electrodes connected to said first memory node, said potential difference being maintained between said first memory node and said second memory node,
- a fifth switching transistor of said second conductivity type connected, between said first bit line and said first memory node and having a gate electrode connected to said word line,
- a sixth switching transistor of said second channel conductivity type connected between said second bit line and said second memory node and having a gate electrode connected to said word line,
- a seventh switching transistor of said second channel conductivity type connected between said common node and a second source of voltage level different from said first source of voltage level and having a gate electrode supplied with a control signal, and
- an eighth switching transistor of said first channel conductivity type connected between said first memory node and said second memory node and having a gate electrode supplied with said control signal.
Dependencies are inferred from the claim text.