Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode

A semiconductor memory device, comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and each pair connecting memory cells on a corresponding column;
• read data bus including a pair of complementary first and second data lines;
• a plurality of pairs of first and second bipolar transistors provided for the respective pairs of first and second bit lines, each of said first bipolar transistors coupled to said first data line in an emitter follower fashion and each of said second bipolar transistors coupled to said second data line in the emitter follower fashion;
• a plurality of first switching means provided corresponding to said plurality of pairs of first and second bit lines and responsive to a column selection signal for transferring potentials of the first and second bit lines of corresponding bit line pairs to respective bases of corresponding first and second bipolar transistors;
• a reference line for transmitting a non-selection level voltage;
• a plurality of second switching means provided corresponding to said plurality of pairs of first and second bit lines and responsive to said column selection signal for turning on complementarily to corresponding first switching means to transfer said non-selection level voltage to bases of corresponding first and second bipolar transistors;
• and,
• generator means for generating onto said reference line as said non-selection level signal a voltage having a level lower than or equal to a low level potential of a selected bit line by said column selection signal in data reading operation mode and a level higher than or equal to a high level potential of the selected bit line in an operation mode other than said data reading operation mode.