Differential carry-save adder and multiplier

A array multiplier comprising:

• an array of 3-2 carry-save adders configured as a multiplier array, wherein the array is divided into a plurality of stages designated in a hierarchy from a first stage where the array receives inputs, which are set-up prior to an evaluation cycle of the array, to a last stage where the sum of the partial products is output, wherein a particular stage includes all 3-2 carry-save adders that receives all its input signals from a previous stage, and wherein at least one input is from the next previous stage, wherein each 3-2 carry-save adder comprises:
• a carry cell including a first pair of cross-coupled transistors connected connected to a first voltage rail, wherein an output of a first transistor of the pair of cross-coupled transistors is coupled to and controls an input of a second transistor of the pair of cross-coupled transistors and an output of the second transistor of the pair of cross-coupled transistors is coupled to and controls an input of the first transistor of the pair of cross-coupled transistors, a first and second precharge transistor, each having a first terminal connected to the first voltage rail and a second terminal connected to an output terminal of the first pair of cross-coupled transistors, and being controlled by a clock, a first enable transistor connected to a second voltage rail, having an output, and having an input controlled by the complement of the clock, and a carry circuit receiving three input signals and three complement input signals and having a carry output and a carry complementary output, wherein the carry output is connected to the output terminal of the first transistor of the first pair of cross-coupled transistors, and the carry complementary output is connected to the output terminal of the second transistor of the first pair of cross-coupled transistors, and further wherein the carry circuit is enabled by the output of the first enable transistor;
• and
• a sum cell including a second pair of cross-coupled transistors connected connected to the first voltage rail, wherein an output of a first transistor of the pair of cross-coupled transistors is coupled to and controls an input of a second transistor of the pair of cross-coupled transistors and an output of the second transistor of the pair of cross-coupled transistors is coupled to and controls an input of the first transistor of the pair of cross-coupled transistors, a third and fourth precharge transistor, each having a first terminal connected to the first voltage rail and a second terminal connected to an output terminal of the first pair of cross-coupled transistors, and being controlled by a clock, a first enable transistor connected to a second voltage rail, having an output, and having an input controlled by the complement of the clock, and a carry circuit receiving the three input signals and the three complement input signals and having a sum output and a sum complementary output, wherein the sum output is connected to the output terminal of the first transistor of the second pair of cross-coupled transistors, and the sum complementary output is connected to the output terminal of the second transistor of the second pair of cross-coupled transistors, and further wherein the carry circuit is enabled by the output of the second enable transistor.

A array multiplier comprising:

• an array of 4-2 carry-save adders configured as a multiplier array, wherein the array is divided into a plurality of stages designated in a hierarchy from a first stage where the array receives inputs, which are set-up prior to an evaluation cycle of the array, to a last stage where the sum of the partial products is output, wherein a particular stage includes all 4-2 carry-save adders that receives all its input signals from a previous stage, and wherein at least one input is from the next previous stage;
• wherein each 4-2 carry-save adder at a particular stage comprises a first 3-2 carry-save adder receiving a first, second and third input, and outputting a first carry and a first sum, and a second 3-2 carry-save adder receiving inputs of the first sum from the first 3-2 carry-save adder, a fourth signal, and a first carry received from a first 3-2 carry-save adder of another 4-2 carry-save adder, and outputting a second carry and a second sum;
• wherein each 3-2 carry-save adder comprises:
• a carry cell including a first pair of cross-coupled transistors connected connected to a first voltage rail, wherein an output of a first transistor of the pair of cross-coupled transistors is coupled to and controls an input of a second transistor of the pair of cross-coupled transistors and an output of the second transistor of the pair of cross-coupled transistors is coupled to and controls an input of the first transistor of the pair of cross-coupled transistors, a first and second precharge transistor, each having a first terminal connected to the first voltage rail and a second terminal connected to an output terminal of the first pair of cross-coupled transistors, and being controlled by a clock, a first enable transistor connected to a second voltage rail, having an output, and having an input controlled by the complement of the clock, and a carry circuit receiving three input signals and three complement input signals and having a carry output and a carry complementary output, wherein the carry output is connected to the output terminal of the first transistor of the first pair of cross-coupled transistors, and the carry complementary output is connected to the output terminal of the second transistor of the first pair of cross-coupled transistors, and further wherein the carry circuit is enabled by the output of the first enable transistor;
• and
• a sum cell including a second pair of cross-coupled transistors connected connected to the first voltage rail, wherein an output of a first transistor of the pair of cross-coupled transistors is coupled to and controls an input of a second transistor of the pair of cross-coupled transistors and an output of the second transistor of the pair of cross-coupled transistors is coupled to and controls an input of the first transistor of the pair of cross-coupled transistors, a third and fourth precharge transistor, each having a first terminal connected to the first voltage rail and a second terminal connected to an output terminal of the first pair of cross-coupled transistors, and being controlled by a clock, a first enable transistor connected to a second voltage rail, having an output, and having an input controlled by the complement of the clock, and a carry circuit receiving the three input signals and the three complement input signals and having a sum output and a sum complementary output, wherein the sum output is connected to the output terminal of the first transistor of the second pair of cross-coupled transistors, and the sum complementary output is connected to the output terminal of the second transistor of the second pair of cross-coupled transistors, and further wherein the carry circuit is enabled by the output of the second enable transistor.