Digital audio delivery in a graphics controller architecture

A graphics/audio controller integrated circuit for processing digital audio data and digital video data stored in a memory means, the memory means including an output port for outputting a series of interleaved digital audio and digital video data, a control port for receiving address signals from a memory control unit, and decoding circuitry for decoding the address signals received by the control port, comprising:

• an audio request signal timer for generating audio request signals;
• a video request signal timer for generating video request signals;
• a control unit responsive to said audio request signals and said video request signals and operative to generate a series of corresponding control signals, wherein the series includes both control signals that cause digital audio data to be retrieved and control signals that cause digital video data to be retrieved from said memory means;
• a temporal storage means for temporarily storing digital data;
• a single conductor data bus for communicating the series of digital data from the memory means to said temporal storage means, the series of digital data including interleaved digital video data and digital audio data;
• and
• means, coupled to said temporal storage means for processing the interleaved digital audio data and digital video data to develop separate analog audio and video signals.

A graphics/audio control system comprising:

• memory means for storing digital audio data and digital video data, the memory means including an output port for, outputting a series of interleaved audio and video digital data to a control port for receiving address signals from a memory control unit, and decoding circuitry for decoding the address signals received by the control port;
• a memory control unit which in response to digital video request signals and digital audio request signals sends a series of address signals to the control port of said memory means, the series alternately including address signals that correspond to digital audio data and digital video data stored in said memory means, said series of address signals being decoded by said decoding circuitry and causing the correspondingly stored digital audio data and digital video data to be interleavedly output via the output port of said memory means;
• a video request signal timer for sending said digital video request signals to the memory control unit;
• an audio request signal timer synchronized with said video request timer for sending said digital audio request signals to the memory control unit in synchronism with said digital video data request signals;
• means for temporal storage of said interleaved audio and video digital data output from said output port of said memory section, said temporal storage means having an input for receiving the interleaved digital data, and an output;
• and
• converter means for receiving the temporarily stored digital data from the output of said temporal storage means, and for converting the video data portion thereof to analog RGB component signals and for converting the audio data portions thereof to left and right analog stereo signals.