Variable length decoder using serial and parallel processing
AssigneeIndustrial Technology Research Institute
InventorsYung-Jung Jan, Yi-Feng Jang
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Abstract
The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.
Claims10
A decoder architecture comprising
- a bit-serial variable length decoder for receiving a variable length coded bit stream and for parsing said bit stream into individual variable length code words,
- buffer means for buffering the individual variable length code words, and
- a plurality of variable length decoders for decoding a plurality of said variable length code words in parallel to generate fixed length code words.
A decoder architecture comprising
- a bit-serial variable length decoder for receiving a variable length coded bit stream and for parsing said bit stream into individual variable length code words without decoding said variable length code words, and
- a plurality of variable length decoders arranged in parallel for decoding said variable length code words.
A method for decoding a variable length coded bit stream comprising the steps of
- using a bit-serial variable length decoder, parsing the bit stream into individual variable length code words, and
- using a plurality of variable length decoders arranged in parallel, decoding said variable length code words.
Dependencies are inferred from the claim text.