US 5,491,443 A · Very low-input capacitance self-biased CMOS buffer amplifier

Abstract

A low-input capacitance self-biased CMOS buffer amplifier (10) which buffers a low-amplitude capacitively coupled output of a sensor to subsequent output circuitry. The buffer amplifier (10) includes a buffer stage (12) which includes an input FET (16) whose gate terminal is connected to the output of the sensor. In order to eliminate the gate-to-source, gate-to-drain and gate-to-substrate capacitances of the input FET (16), various FETs are associated with the buffer stage (12) are interconnected such that the integrity of the input signal is maintained. An output FET (18) has its source terminal connected to the source terminal of the input FET (16). Additionally, a tail cascoded current source (20, 22) is connected to the source terminals of the input and output FETs (16, 18) such that the gate-to-source voltages of these two FETs (16, 18) is the same. The gate terminal and the drain terminal of the output FET (18) are connected such that the input and output FETs (16, 18) act as unit to gain amplifier. The gate terminal of the output FET (18) is connected to two other FETs (24, 26) which transfer the gate-to-drain voltage of the output FET (18) to the drain terminal of the input FET (16). In order to eliminate the gate-to-substrate capacitance, the gate terminal of the input FET (16) is shielded from the substrate by a bottom metal layer (28) of this FET (16). Several self-biasing features are provided to interconnect the FETs in the circuit such that a common current flow is maintained throughout the buffer stage (12).

Claims35

Dependent claims

A buffer for buffering a capacitive output of a sensor, said buffer comprising:

a first field effect transistor (FET) including a gate terminal, a source terminal and a drain terminal, said first FET acting as an input FET wherein an output signal from the sensor is applied to the gate-terminal of the first FET as an input signal;
a second FET including a gate terminal, a source terminal and a drain terminal, said second FET acting as an output FET, wherein the source terminal of the first FET is connected to the source terminal of the second FET, and the gate terminal and the drain terminal of the second FET are connected together;
a third FET including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the third FET is connected to the drain terminal of the second FET and the drain terminal of the third FET is connected to a voltage potential;
and
a fourth FET including a gate terminal, a source terminal and a drain terminal, wherein the source terminal of the third FET is connected to the source terminal of the fourth FET and the gate and drain terminals of the fourth FET are connected to the drain terminal of the first FET, said third and fourth FETs transferring the voltage potential at the gate terminal of the second FET to the drain terminal of the first FET such that the first and second FETs act as a unity gain amplifier.

2 more elements

A buffer for buffering a capacitive output of a sensor, said buffer comprising:

a first field effect transistor (FET) including a gate terminal, a source terminal and a drain terminal, said first FET acting as an input FET wherein an output signal from the sensor is applied to the gate terminal of the first FET as an input signal;
a second FET including a gate terminal, a source terminal and a drain terminal, said second FET being a biasing FET that biases the gate terminal of the first FET, wherein the gate terminal of the first FET .is connected to a terminal selected from the group of terminals consisting of the drain terminal of the second FET and the source terminal of the second FET;
and
a tail cascoded current source, said tail cascoded current source including a third FET and a fourth FET each including a at least, a source terminal and a drain terminal, wherein the source terminal of the third FET is connected to a voltage potential, the drain terminal of the third FET is connected to the source terminal of the fourth FET, and the drain terminal of the fourth FET is connected to the source terminal of the first FET.

1 more element

A buffer amplifier for buffering and amplifying a capacitive output of a sensor, said buffer amplifier comprising:

a first field effect transistor (FET) including a gate terminal, a source terminal and a drain terminal, said first FET acting as an input FET wherein an output signal from the sensor is applied to the gate terminal of the first FET as an input signal, said drain terminal of the first FET being connected to a shielding layer;
a second FET including a gate terminal, a source terminal and a drain terminal, wherein the source terminal of the second FET is connected to the source terminal of the first FET, and the gate terminal and the drain terminal of the second FET are connected such that the first and second FETs act as a unity gain amplifier so that a signal at the gate-terminal of the second FET substantially coincides with the input signal applied at the gate terminal of the first FET;
a tail cascoded current source, said tail cascoded current source including a third FET and a fourth FET each including a gate terminal, a source terminal and a drain terminal, wherein the source terminal of the third FET is connected to a voltage source, the drain terminal of the third FET is connected to the source terminal of the fourth FET and the drain terminal of the fourth FET is connected to the source terminals of the first and second FETs;
a fifth FET including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the fifth FET is connected to the drain terminal of the second FET, and the drain terminal of the fifth FET is connected to the voltage source;
a sixth FET including a gate terminal, a source terminal and a drain terminal, wherein the source terminal of the sixth FET is connected to the source terminal of the fifth FET, and the gate and drain terminals of the sixth FET are connected to the drain terminal of the first FET;
a seventh FET including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the seventh FET is connected to one of the group consisting of the gate terminal Of the first FET, the source terminal of the first FET and a voltage source;
an eighth FET including a gate terminal, a source terminal and a drain terminal, wherein the drain and gate terminals of the eighth FET are connected to the voltage source and the source terminal of the eighth FET is connected to a ground potential;
a ninth FET including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the ninth FET is connected to the gate terminal of the eighth FET, the drain terminal of the ninth FET is connected to the source terminals of the fifth and sixth FETs, and the source terminal of the ninth FET is connected to a ground potential;
a tenth FET including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal of the tenth FET is connected to the gate terminal of the ninth FET, the drain terminal of the tenth FET is connected to the drain terminal of the second FET, and the source terminal of the tenth FET is connected to a ground potential;
and
an amplifier circuit, said amplifier circuit receiving the output signal from the gate terminal of the second FET and providing an amplified output signal.

8 more elements

A buffer for buffering a capacitive output of a sensor, said buffer comprising:

a first field effect transistor (FET) including a gate terminal, a source terminal and a drain terminal, said first FET acting as an input FET wherein an output signal from the sensor is applied to the gate terminal of the first FET as an input signal;
a second FET including a gate terminal, a source terminal and a drain terminal, said second FET being a biasing FET that biases the first FET, wherein the gate terminal of the second FET is connected to the source terminal of the first FET;
and
a tail cascoded current source including a third FET and a fourth FET each including a gate terminal, a source terminal and a drain terminal, wherein the source terminal of the third FET is connected to a voltage potential, the drain terminal of the third FET is connected to the source terminal of the fourth FET, and the drain terminal of the fourth FET is connected to the source terminal of the first FET.

1 more element

Dependencies are inferred from the claim text.

Very low-input capacitance self-biased CMOS buffer amplifier

Life of this patent

Very low-input capacitance self-biased CMOS buffer amplifier

Life of this patent

Abstract

Claims35