Multiple frequency output clock generator system
AssigneeTandem Computers Incorporated
InventorsRussell N. Mirov, Duc N. Le, Frank Mikalauskas, C. John Grebenkemper, Kinying Kwan
Life of this patent
Estimating the term…
Abstract
A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.
Claims5
A clock generator circuit for producing a plurality of clock signals, the clock generator comprising:
- a source of a master clock signal;
- a delay element coupled to receive the master clock signal to produce a delayed clock signal;
- a frequency divider that receives the delayed clock signal to produce therefrom a divided clock signal;
- a first flip-flop having a data input coupled to receive the divided clock signal, a clock input receiving the master clock signal, and an output;
- and
- for each of a first predetermined number of the plurality of clock signals having a first frequency,
- a second flip-flop having a data input receiving the output of the first flip-flop, a clock input receiving the delayed clock signal, and an output whereat a corresponding one of said first predetermined number of the plurality of clock signals is provided.
Dependencies are inferred from the claim text.