Automatic clock duty cycle adjusting circuit

Abstract

A circuit for automatically adjusting duty cycle of an output clock signal is provided. The circuit comprises a monostable multivibrator for receiving an input clock signal at its clock terminal and outputting an output clock signal, a frequency dividing circuit for dividing down the input clock signal by 1/N, an inverter for inverting an output of the frequency dividing circuit, an integrating circuit for receiving the output clock signal, a comparator for receiving an output of the integrating circuit and a reference voltage corresponding to a desired duty cycle, a D-type flip-flop for receiving an output of the comparator at its data terminal and an output of the inverter at its clock terminal, an AND gate for receiving an inverse output of the D-type flip-flop and the output of the frequency dividing circuit, and a counter for receiving a reset signal at its reset terminal and an output of the AND gate at its clock terminal, and for counting a set data which is input to the monostable multivibrator, wherein the monostable multivibrator outputs the output clock signal having a pulse width corresponding to the set data.

Dependencies are inferred from the claim text.