Compensated CMOS driver circuit with reduced DC losses

An integrated circuit providing a circuit output which is compensated for variations in the process conditions employed in circuit construction, said integrated circuit comprising at least a first and second FET device and a voltage divider, said first FET device providing an output signal in response to the circuit input signal to said integrated circuit, and said second FET device providing an output signal in response to the output of said voltage divider;

• each said first and second FET devices having at least one performance characteristic which varies in the same manner with variations in at least one process condition of said circuit such that said output signals of each of said first and second FET devices have at least one output signal characteristic which is changed by variations in said one process condition;
• said first and second FET devices having their outputs merged such that said one output signal characteristic of said second FET device acts in opposition to that of said first FET device, and said second FET device being constructed to be more responsive to variations in said one process condition than said first FET device and to have a weaker output signal than said first FET device whereby said merged output of said first and second FET devices is maintained relatively consistent irrespective of variations in said one process condition;
• and
• said voltage divider including a third FET device having its gate coupled to said circuit output so that said third FET is rendered nonconductive to thereby turn off said voltage divider when said circuit output is above the threshold voltage of said third FET device.

An integrated circuit providing a circuit output which is compensated for variations in the process conditions employed in circuit construction, said integrated circuit comprising at least a first and second FET device and a voltage divider, said first FET device providing an output signal in response to the circuit input signal to said integrated circuit, and said second FET device providing an output signal in response to the output of said voltage divider;

• each said first and second FET devices having at least one performance characteristic which varies in the same manner with variations in at least one process condition of said circuit such that said output signals of each of said first and second FET devices have at least one output signal characteristic which is changed by variations in said one process condition;
• said first and second FET devices having their outputs merged such that said one output signal characteristic of said second FET device acts in opposition to that of said first FET device, and said second FET device being constructed to be more responsive to variations in said one process condition than said first FET device and to have a weaker output signal than said first FET device whereby said merged output of said first and second FET devices is maintained relatively consistent irrespective of variations in said one process condition;
• and
• said voltage divider including a third FET device having its gate coupled to said circuit output so that said third FET is rendered nonconductive to thereby turn off said voltage divider when said circuit output is above the threshold voltage of said third FET device, said first FET device is provided within a circuit branch which is placed in standby condition in response to an enable signal, said voltage divider includes an additional FET device connected in series with said third FET device, and said additional FET device is rendered conductive in response to said enable signal to place said voltage divider in standby condition.

An integrated circuit providing a circuit output which is compensated for variations in the process conditions employed in circuit-construction, said integrated circuit comprising at least a first and second FET device and a voltage divider, said first FET device providing an output signal in response to the circuit input signal to said integrated circuit, and said second FET device providing an output signal in response to the output of said voltage divider;

• each said first and second FET devices having at least one performance characteristic which varies in the same manner with variations in at least one process condition of said circuit such that said output signals of each of said first and second FET devices have at least one output signal characteristic which is changed by variations in said one process condition;
• said first and second FET devices having their outputs merged such that said one output signal characteristic of said second FET device acts in opposition to that of said first FET device, and said second FET device being constructed to be more responsive to variations in said one process condition than said first FET device and to have a weaker output signal than said first FET device whereby said merged output of said first and second FET devices is maintained relatively consistent irrespective of variations in said one process condition;
• and
• said voltage divider including a third FET device having its gate coupled to said circuit output so that said third FET is rendered nonconductive to thereby turn off said voltage divider when said circuit output is above the threshold voltage of said third FET device, said voltage divider includes another FET device connected in series with said third FET device, and said another FET device is rendered conductive in response to said circuit input signal.