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AssigneeSamsung Electronics Co., Ltd.
InventorsZin-Suk Mun, Myung-Ho Bae
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A data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between the complementary bit lines, a sense amplifier equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective ones of the second capacitors. Selected ones of the first and/or second fuses can be selectively blown to thereby couple selected ones of the first and/or second capacitors to the sensing control nodes of the PMOS and NMOS sense amplifiers, respectively, to thereby equalize the capacitances of the sensing control nodes even when they have different parasitic capacitances.
A data sensing circuit for a semiconductor memory device having complementary bit lines, comprising:
Dependencies are inferred from the claim text.