US 5,491,434 A · Circuit and method of differential amplitude detection

Abstract

A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.

Claims19

Dependent claims

A differential amplitude detection circuit, comprising:

a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal;
a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal;
a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component of said differential input signal;
a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component of said differential input signal;
and
a summing circuit having first and second inputs respectively coupled for receiving said first and second peak signals and having an output coupled to an output node of the differential amplitude detection circuit for providing a signal representative of an amplitude of said differential input signal.

3 more elements

A differential amplitude detection circuit, comprising:

a first peak detector circuit having an input coupled for receiving a first component of a differential input signal and having an output for providing a first peak signal;
a first holding capacitor coupled to said output of said first peak detector circuit;
a first current load circuit coupled to said output of said first peak detector circuit for tracking a decreasing offset component of said first component;
a first buffer amplifier having an input coupled for receiving said first peak signal and having an output;
a first resistor coupled between said output of said first buffer amplifier and a first output node;
a second peak detector circuit having an input coupled for receiving a second component of said differential input signal and having an output for providing a second peak signal;
a second holding capacitor coupled to said output of said second peak detector circuit;
a second current load circuit coupled to said output of said second peak detector circuit for tracking a decreasing offset component of said second component;
a second buffer amplifier having an input coupled for receiving said second peak signal and having an output;
and
a second resistor coupled between said output of said second buffer amplifier and said first output node.

8 more elements

Dependencies are inferred from the claim text.

Circuit and method of differential amplitude detection

Life of this patent

Circuit and method of differential amplitude detection

Life of this patent

Abstract

Claims19