Self-aligned contact formation
AssigneeSGS-Thomson Microelectronics S.A.
InventorsChe C. Wei, Chiara Zaccherini, Robert O. Miller, Girish A. Dixit
Life of this patent
Estimating the term…
Abstract
A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
Claims10
An integrated circuit structure, comprising:
- a device layer having conducting regions therein;
- an insulating layer over said device layer, said insulating layer having openings therein which expose selected conducting regions therethrough, wherein the openings have sidewalls;
- a patterned polycrystalline silicon interconnect layer overlying said insulating layer and having portions adjacent the insulating layer openings, wherein the patterned polycrystalline silicon interconnect layer has a top and sides, and wherein the adjacent portions have a sidewall aligned with an opening sidewall and are separated from the conducting regions by said insulating layer;
- metallic conducting regions in contact with and covering the top and sides of said interconnect layer, wherein said metallic conducting regions adjacent the insulating layer openings extend into and cover such openings, and wherein said interconnect layer and said metallic conducting regions define conductive signal lines;
- a lower insulating layer between said device layer and said insulating layer;
- and
- a lower patterned polycrystalline silicon interconnect layer between said lower insulating layer and said insulating layer;
- wherein portions of said lower interconnect layer are also exposed in the insulating layer openings, whereby said metallic conducting regions which extend into the openings also make contact with the lower interconnect layer exposed portions.
An integrated circuit structure, comprising:
- a device layer having conducting regions therein;
- a first insulating layer overlying said device layer;
- a patterned polycrystalline silicon interconnect layer overlying said first insulating layer;
- a second insulating layer overlying said interconnect layer and said first insulating layer;
- a plurality of openings through said first and second insulating layers to expose selected conducting regions, wherein portions of said patterned polycrystalline silicon interconnect layer are exposed in the opening, and are separated from the conducting regions by said first insulating layer;
- metallic conducting regions within said openings and forming conducting regions between said interconnect and said device layer conducting regions, wherein said metallic conducting regions do not extend beyond the openings;
- a lower insulating layer between said device layer and said first insulating layer;
- and
- a lower patterned polycrystalline silicon interconnect layer between said lower insulating layer and said first insulating layer;
- wherein portions of said lower interconnect layer are also exposed in said openings, whereby said metallic conducting regions also make contact with the lower interconnect layer exposed portions.
Dependencies are inferred from the claim text.