Method for fabricating DRAM cells having fin-type stacked storage capacitors

A method for fabricating dynamic random access memory cells on a semiconductor substrate having field effect transistors and storage capacitors, comprising the steps of:

• selectively forming a field oxide on portions of a silicon substrate while providing device areas for fabricating field effect transistors;
• forming a gate dielectric layer on said substrate in said device areas;
• depositing a first polysilicon layer on said field oxide areas and said device areas;
• depositing a first insulating layer on said first polysilicon layer;
• masking and etching said first insulating layer and said first polysilicon layer, thereby forming gate electrodes on said device areas and electrically conducting word lines elsewhere on said substrate;
• forming source/drain regions within said device areas adjacent to said gate electrodes by implantation;
• depositing a second insulating layer on said substrate;
• and
• anisotropically etching back said second insulating layer to said source/drain regions and thereby forming sidewall spacers on sidewalls of said gate electrodes and said word lines;
• depositing a third insulating layer on said substrate over said source/drain regions and elsewhere on said substrate;
• and
• selectively forming contact openings in said third insulating layer to one of the two said source/drain regions of each field effect transistor;
• depositing a second polysilicon layer on said substrate, making electrical contact to said source/drain regions in said contact openings;
• and
• depositing a metal silicide layer on said second polysilicon layer;
• patterning by masking and etching said metal silicide layer and said second polysilicon layer and thereby forming electrically conducting bit lines contacting said source/drains of said field effect transistors;
• depositing a fourth insulating layer on said substrate and forming said storage capacitor by,
• forming a contact opening in said fourth and third insulating layer exposing a second source/drain region of each of said field effect transistors,
• conformally depositing a third polysilicon layer on said substrate without filing said contact openings to said source/drain regions, and thereby making electrical contact by out diffusing dopants from said third polysilicon layer to said source/drain regions in said contact openings in said third and fourth insulating layers,
• depositing a fifth insulating layer and thereby providing a sacrificial silicon oxide layer for forming said storage capacitors,
• masking and etching contact openings in said fifth insulating layer exposing said third polysilicon layer only and directly over said second source/drain regions of said field effect transistors,
• depositing a fourth polysilicon layer over said fifth insulating layer and making electrical contact to said third polysilicon layer through said contact openings in said fifth insulating layer, and wherein said fourth polysilicon layer fills said contact openings in said fifth insulating layer,
• patterning said fourth polysilicon layer over said fifth insulating layer and thereby defining bottom electrode over each of said dynamic random access memory cell areas,
• etching isotropically and removing said fifth insulating layer completely from said substrate,
• etching anisotropically and patterning said third polysilicon layer, and forming bottom capacitor electrodes having a fin shape,
• forming a capacitor dielectric layer on the surface of said bottom capacitor electrodes,
• depositing a fifth polysilicon layer on said substrate and forming the top capacitor electrode, and thereby completing said dynamic random access memory cells having said storage capacitors.