Apparatus and method for entry allocation for a resource buffer

An apparatus for allocating vacancies of a buffer resource to instructions and instruction data within a pipelined superscalar microprocessor, said apparatus comprising:

• a deallocation vector for indicating vacancies within said buffer resource for a current allocation cycle;
• circuitry for separating said deallocation vector into a first vector portion and a second vector portion;
• first vacancy location circuitry coupled to receive said first vector portion and generating therefrom a first enable vector and a second enable vector for said current allocation cycle, said first and said second enable vector each indicating an entry into said resource buffer for storage of instruction information relating to a first instruction and a second instruction, respectively;
• and
• second vacancy location circuitry, operable simultaneous with said first vacancy location circuitry, coupled to receive said second vector portion and generating therefrom a third enable vector and a fourth enable vector, said third and said fourth enable vector each indicating an entry into said resource buffer for storage of instruction information relating to a third instruction and a fourth instruction, respectively.

A computer system comprising:

• a bus for providing a communication pathway;
• a memory coupled to said bus for storing instructions and program information;
• a user interface coupled to said bus for receiving information and for communicating information;
• and
• a pipelined superscalar processor coupled to said bus for executing instructions and processing data, said processor comprising allocation circuitry for allocating entries of a resource buffer for storage of instructions information relating a set of instructions into said buffer resource, said allocation circuitry comprising:
• a deallocation vector for indicating vacant entries within said buffer resource;
• circuitry for separating said deallocation vector into a first vector portion and a second vector portion;
• vacancy location circuitry coupled to receive a vector portion of either said first vector portion or said second vector portion and generating for a current allocation cycle at least one enable vector indicating a vacant entry of said buffer resource for storage of instruction information relating to one of said instructions, said vacancy location circuitry comprising:
• processing logic for examining separate portions of said vector portion for vacancies and for each of said separate portions examined, for generating a plurality of bitmaps associated with each separate portion;
• and
• multiplexing logic for multiplexing each of said bitmaps based on a priority reference bit pointer of said vector portion and generating therefrom said enable vector.

In a pipelined or superscalar microprocessor including an buffer resource, and a deallocation vector for indicating vacant entries within said buffer resource for storage of information relating to a set of issued instructions, an apparatus for allocating highest priority vacancies within said buffer resource, said apparatus comprising:

• processing logic for examining separate portions of said deallocation vector for vacancies and for each issued instruction, generating for a given allocation cycle a set of bitmap vectors, said set of bitmap vectors comprising separate bitmap vectors corresponding to each of said separate portions of said deallocation vector;
• multiplexing logic for multiplexing each of said bitmap vectors to generate an enable vector for each of said set of issued instructions, said enable vector indicating a vacant storage entry within said buffer resource, said multiplexing logic coupled to said processing logic, wherein said processing logic and said multiplexing logic process said deallocation vector based on a priority bit pointer to said deallocation vector;
• and
• logic for updating said priority bit pointer for individual allocation cycles.

A computer system comprising:

• a bus for providing a communication pathway;
• a memory coupled to said bus for storing instructions and program information;
• a user interface coupled to said bus for receiving information and for communicating information;
• and
• a pipelined superscalar processor coupled to said bus for executing instructions and processing data, said processor comprising allocation circuitry for allocating highest priority vacancies within a resource buffer for storage of a set of issued instructions, said allocation circuitry comprising:
• processing logic for examining separate portions of said deallocation vector for vacancies and for each issued instruction, generating for a given allocation cycle a set of bitmap vectors, said set of bitmap vectors comprising separate bitmap vectors corresponding to each of said separate portions of said deallocation vector;
• multiplexing logic for multiplexing each of said bitmap vectors to generate an enable vector for each of said set of issued instructions, said enable vector indicating a vacant storage entry within said buffer resource, said multiplexing logic coupled to said processing logic, wherein said processing logic and said multiplexing logic process said deallocation vector based on a priority bit pointer to said deallocation vector;
• and
• logic for updating said priority bit pointer for individual allocation cycles.

Within a pipelined or superscalar microprocessor, a method of assigning vacant entries of a buffer resource for storage of instruction data relating to instructions, said method comprising the steps of:

• receiving a deallocation vector indicating vacant entries of said buffer resource;
• separating said deallocation vector into a first vector portion and a second vector portion;
• receiving an input vector portion of either said first vector portion or said second vector and generating therefrom at least one enable vector indicating a vacant entry of said buffer resource for storage of instruction information for one of said instructions, said step of generating comprising the steps of:
• examining separate portions of said input vector portion for vacancies and for each of said separate portions examined, generating for a given allocation cycle a plurality of bitmaps associated with each separate portion;
• and
• multiplexing said bitmaps based on a priority reference bit pointer of said vector portion and selecting one of said bitmaps to generate an enable vector therefrom corresponding to an instruction of said instructions.

In a pipelined or superscalar microprocessor including a buffer resource, and a deallocation vector indicating vacant entries of said buffer resource for storage of a set of issued instructions, a method of allocating highest priority vacancies within said buffer resource to said set of issued instructions, said method comprising the steps of:

• examining separate portions of said deallocation vector for vacancies and for each issued instruction generating a set of bitmap vectors, said set of bitmap vectors comprising different bitmap vectors corresponding to each of said separate portions of said deallocation vector;
• multiplexing each of said bitmap vectors to generate an enable vector for each of said set of issued instructions, said enable vector for indicating a vacant storage location within said buffer resource, said step of multiplexing receiving information from said step of examining, wherein said step of examining and multiplexing process said deallocation vector based on a priority bit pointer to said deallocation vector;
• and
• updating said priority bit pointer for individual allocation cycles.