Digital computation integrated circuit

A digital computation integrated circuit comprising:

• first address generating means for generating a first address signal indicating a first address that sequentially follows a preceding address;
• second address generating means, in response to a control signal, for generating a second address signal indicating a second address that does not sequentially follow the preceding address;
• address selecting means for selecting the first address signal in response to a first selection signal, and for selecting the second address signal in response to a second selection signal;
• instruction memory means for storing instruction data;
• store address designating means, in response to the selected one of the first and second address signals, for designating a storing address of the instruction data in the instruction memory means, the instruction memory means outputting the instruction data as a result thereof;
• instruction decode means for receiving the instruction data outputted from said instruction memory means, for converting the instruction data into the control signal to be outputted when the instruction data represents a branch instruction and for outputting either the first selection signal indicating that the instruction data represents sequential progress of a program or the second selection signal indicating that the instruction data representing the branch instruction;
• address accepting means, in response to the second selection signal, for accepting a store address and a jump destination address included in the instruction data representing the branch instruction;
• store address generating means for increasing the store address when said address accepting means has received the store address and the jump destination address;
• and
• address memory means for storing the store address and the jump destination address accepted by the address accepting means in the address increased and outputted by the store address generating means.

A digital computation integrated circuit comprising:

• first address generating means for generating a first address signal indicating a first address that sequentially follows a preceding address;
• second address generating means, in response to a control signal, for generating a second address signal indicating a second address that does not sequentially follow the preceding address;
• address selecting means, for selecting the first address signal in response to a first selection signal, and for selecting the second address signal in response to a second selection signal;
• instruction memory means for storing instruction data;
• store address designating means, in response to the selected one of the first and second address signal, for designating a storing address of the instruction data in the instruction memory means, the instruction memory means outputting the instruction data as result thereof;
• instruction decode means for receiving the instruction data outputted from said instruction memory means, for converting the instruction data into the control signal to be outputted and outputting a repetition signal when the instruction data represents a repetition instruction and for outputting either the first selection signal indicating that the instruction data represents sequential progress of a program or the second selection signal indicating that the instruction data represents the repetition instruction;
• count means, in response to the repetition signal, for counting a number of repetition by the repetition instruction;
• store address generating means, in response to the repetition signal, for generating an address where the number of repetition is stored;
• and
• address memory means for storing said address of said repetition instruction data and the number of repetition of the count means.